Adaptive Trace Width in Multilayer Substrates for Signal Integrity
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Solution Overview
Problem
The design of multilayer substrate packages faces challenges in achieving optimal signal integrity, yield, and manufacturability due to physics-induced nonuniformities in trace thickness and dielectric layers, leading to compromised performance and increased manufacturing costs.
Innovation Solution
An adaptive design approach that uses a mechanical model to predict and modify trace variables such as trace width, thickness, and dielectric thickness to compensate for manufacturing-induced variations, allowing for optimized signal integrity and yield through dynamic data communication between signal integrity, yield, and manufacturing models.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If uniform trace width and dielectric thickness are used throughout the substrate, then manufacturing simplicity is maintained, but signal integrity deteriorates due to physics-induced nonuniformities in trace thickness and dielectric layers
Solution Approach 1:
The patent applies local quality by varying the trace width at different locations across the substrate. Specifically, the trace width is adjusted in different regions (e.g., first region vs. second region) to compensate for local variations in dielectric thickness and trace thickness. This ensures that the characteristic impedance remains consistent throughout the substrate despite manufacturing nonuniformities, thereby improving signal integrity without requiring uniform trace dimensions.
Solution Approach 2:
The patent changes the geometric parameter of trace width to compensate for manufacturing variations. By modifying the trace width parameter in response to measured or predicted variations in dielectric and trace thickness, the design maintains consistent electrical characteristics. This parameter adjustment allows the system to adapt to manufacturing nonuniformities while preserving signal integrity.
2Manufacturing precision
If trace width is varied to compensate for manufacturing nonuniformities, then signal integrity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements preliminary action by pre-determining the nonuniform trace width pattern during the design phase based on predicted or measured manufacturing variations. The varying trace width is built into the substrate design before manufacturing, allowing compensation for expected nonuniformities without requiring complex real-time adjustments during production. This approach maintains signal integrity while keeping the manufacturing process relatively simple.
3Speed
If higher signal speeds and bandwidth are achieved through heterogeneous packaging, then performance is improved, but design complexity and yield challenges increase
Solution Approach 1:
The patent applies local quality by tailoring the trace width in different regions of the substrate to accommodate high-speed signaling requirements. By locally optimizing trace dimensions in regions carrying high-speed signals (such as DDR or PCIE regions), the design achieves improved signal integrity and performance while managing the complexity through region-specific adjustments rather than uniform changes across the entire substrate.
Data Source
AI summary
A package substrate stack modeler includes a manufacturing modeler, configured to generate a model of a real package substrate stack based on an ideal design of the package substrate stack; a signal integrity model, configured to determine a signal integrity of a metal trace of the real package substrate stack; and a yield model, configured to determine a yield of the real package substrate stack; wherein the metal trace comprises a first value of a trace variable; further comprising a processor, configured to select a second value of the trace variable of the metal trace based on the determined signal integrity of the metal trace or the determined yield of the package substrate stack model.