Adaptive Voltage Regulation for Standard Cell Timing
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Solution Overview
Problem
Semiconductor integrated circuits face challenges in meeting timing requirements due to manufacturing process variations, power supply voltage variations, and temperature variations, leading to increased chip size and power requirements when using automated design tools that account for these variations by adding more components or increasing power consumption.
Innovation Solution
The method involves specifying requirements for integrated circuits that include a signal path for speed comparison, setting a higher voltage for the slow corner, and using dynamic voltage scaling to determine if the circuit design meets timing requirements for both slow and fast corners, incorporating an adaptive voltage regulation circuit to adjust power supply voltages based on process and temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If automated design tools add more components or increase power consumption to account for timing variations, then timing requirements are met, but chip area and power consumption increase
Solution Approach 1:
The patent applies dynamic voltage scaling by implementing an adaptive voltage regulator that adjusts the voltage level based on detected circuit speed characteristics. Fast circuits operate at lower voltages to reduce power consumption, while slow circuits receive higher voltages to meet timing requirements. This dynamic adaptation eliminates the need for static over-provisioning of components, thereby reducing chip area while maintaining timing compliance across process variations.
Solution Approach 2:
The patent changes the voltage parameter dynamically based on circuit performance characteristics. By detecting whether circuits operate fast or slow and adjusting the supply voltage accordingly, the system optimizes the trade-off between timing compliance and power/area consumption. This parameter adjustment allows the same physical circuit to meet timing requirements under varying conditions without adding extra components.
2Reliability
If automated design tools add more components or increase power consumption to account for timing variations, then timing requirements are met, but power consumption increases
Solution Approach 1:
The patent implements dynamic voltage scaling where the power consumption is adjusted based on actual circuit performance. Fast circuits that already meet timing requirements operate at reduced voltage levels, significantly lowering their power consumption. Slow circuits receive increased voltage only when necessary to meet timing constraints. This dynamic approach replaces static power over-provisioning with adaptive power management, reducing overall power consumption while maintaining timing compliance.
Solution Approach 2:
The patent changes the voltage parameter dynamically based on circuit speed detection. By adjusting the supply voltage to match actual circuit performance characteristics, the system optimizes power consumption. Circuits that are inherently fast consume less power at lower voltages, while circuits needing timing assistance receive higher voltages only when required, eliminating wasteful uniform power over-provisioning across the entire chip.
3Reliability
If larger components or additional components are used to meet timing goals, then timing requirements are satisfied, but chip area increases
Solution Approach 1:
The patent uses dynamic voltage scaling to adjust circuit performance rather than relying on static component sizing. By detecting circuit speed and adjusting voltage accordingly, fast circuits can use smaller components while still meeting timing requirements when needed. This eliminates the need to design for the worst-case slow scenario across all circuits, allowing area optimization for fast circuits without compromising timing compliance.
Data Source
AI summary
A semiconductor integrated circuit including a circuit for adaptive power supply regulation and designed using a process that increases operating speed used for characterizing circuit operation at a slow corner. In some embodiments a slow corner voltage is set to a higher than expected level for timing analysis performed by automated design tools.