Adaptive Wire Routing for Chiplet Interconnection Misalignment
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Solution Overview
Problem
Existing methods for forming active-matrix control elements in flat-panel display devices face challenges with non-uniformity and alignment issues due to the use of thin-film silicon, leading to lower performance and yield in large-area substrates.
Innovation Solution
The use of differently shaped wires for corresponding chiplets with unique connection pads allows for correct connections and improved yields, even with misaligned chiplets, by employing adaptive interconnections and dynamic path determination using imaging sensors and routing software.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithographic techniques are used to interconnect chiplets on large substrates, then manufacturing process simplicity is maintained, but alignment precision deteriorates due to positional variability and rotational skew
Solution Approach 1:
The patent implements dynamic wire routing where the path shape is determined based on actual chiplet positions detected by imaging sensors. The routing software generates adaptive interconnection paths that adjust to manufacturing tolerances and misalignments, transforming the static photolithographic approach into a dynamic, adaptive system that achieves precise alignment despite positional variability and rotational skew
Solution Approach 2:
The patent replaces the mechanical photolithographic alignment system with an optical-imaging-based detection and software-based routing system. Imaging sensors capture chiplet positions, and routing software computes adaptive wire paths, substituting the rigid mechanical alignment process with a flexible optical-and-computational approach that achieves superior alignment precision
2Manufacturing precision
If chiplets are mounted with strict pre-determined locations and orientations, then interconnection accuracy is improved, but manufacturing yield deteriorates due to sensitivity to misalignment
Solution Approach 1:
The patent implements a feedback mechanism where imaging sensors detect the actual positions and orientations of mounted chiplets, and this information is fed back to the routing software. The software then generates adaptive wire routing paths that compensate for detected misalignments, transforming the open-loop photolithographic process into a closed-loop system that maintains high interconnection accuracy while tolerating manufacturing variations
Solution Approach 2:
The patent changes the routing parameters dynamically based on detected chiplet positions. Instead of using fixed photolithographic patterns, the system adjusts wire path shapes, lengths, and geometries to accommodate actual chiplet placements within manufacturing tolerances, thereby maintaining interconnection accuracy while improving manufacturing yield
3Ease of manufacture
If thin-film silicon is used for active-matrix control elements, then ease of manufacture is improved, but device performance deteriorates due to non-uniformity and lower transistor performance
Solution Approach 1:
The patent segments the control element fabrication into two independent parts: chiplets fabricated using conventional thin-film silicon techniques on separate substrates, and the final display substrate. This segmentation allows each part to be optimized independently - chiplets can use easy-to-manufacture thin-film processes while achieving high performance through precise positioning and adaptive interconnection on the final substrate
Data Source
AI summary
An active-matrix device includes a device substrate including a plurality of pixels formed thereon, each pixel having a separate control electrode, a plurality of chiplets having at least first and second corresponding chiplets disposed at different locations over the device substrate, a plurality of wires formed over the device substrate, each wire being connected to a connection pad and to a different pixel control electrode, and wherein the shape of at least one of the wires connecting a connection pad for the first chiplet is different from the shape of at least one of the wires connecting a corresponding connection pad for the second chiplet.