Adaptive Write Assist Circuit for SRAM Power Optimization

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Solution Overview

Problem

Static Write Assist (WA) circuits in SRAM bit-cells are inefficient due to fixed power supply collapsing settings, leading to increased power consumption, write time, and bit-cell size, which fail to account for varying operating conditions like voltage, temperature, and frequency, resulting in write failure risks and reliability concerns.

Innovation Solution

The implementation of adaptive WA circuits that dynamically modulate power supply collapse duration and magnitude, as well as Negative Bit-Line (NBL) WA techniques, based on real-time operating conditions such as voltage and temperature, to optimize write assist operations and reduce power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If static Write Assist circuits are used with fixed power supply collapsing settings, then the SRAM bit-cell can meet basic write operations, but power consumption increases and write time increases

Engineering Contradiction:
Improvewrite operation reliabilityVSAvoidwrite power consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by transitioning from static Write Assist circuits with fixed power supply collapsing settings to dynamic Write Assist circuits that adapt their operation based on real-time operating conditions. The circuit monitors voltage, temperature, and frequency parameters and dynamically adjusts the power supply collapse magnitude and duration to match current operating conditions, thereby reducing unnecessary power consumption while maintaining write operation reliability across varying conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements parameter changes by modifying the power supply voltage collapse characteristics (magnitude and duration) based on detected operating conditions. When voltage, temperature, or frequency parameters fall within specific ranges, the circuit adjusts the Write Assist parameters accordingly, enabling optimal power consumption and write performance for each operating condition rather than using a fixed conservative setting.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If static Write Assist circuits are used with fixed power supply collapsing settings, then the SRAM bit-cell can meet basic write operations, but write time increases

Engineering Contradiction:
Improvewrite operation reliabilityVSAvoidwrite time
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent applies dynamics by transitioning from static Write Assist circuits with fixed power supply collapsing settings to dynamic Write Assist circuits that adapt their operation based on real-time operating conditions. The circuit monitors voltage, temperature, and frequency parameters and dynamically adjusts the power supply collapse magnitude and duration to match current operating conditions, thereby reducing unnecessary power consumption while maintaining write operation reliability across varying conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements parameter changes by modifying the power supply voltage collapse characteristics (magnitude and duration) based on detected operating conditions. When voltage, temperature, or frequency parameters fall within specific ranges, the circuit adjusts the Write Assist parameters accordingly, enabling optimal power consumption and write performance for each operating condition rather than using a fixed conservative setting.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If static Write Assist circuits are used, then the SRAM bit-cell can perform write operations, but the bit-cell size increases

Engineering Contradiction:
Improvewrite operation reliabilityVSAvoidSRAM bit-cell area
Core Design Contradiction:
ReliabilityVSArea of moving object

Solution Approach 1:

The patent applies universality by designing a Write Assist circuit that can operate effectively across a wide range of operating conditions (voltage, temperature, frequency) through dynamic adaptation. This multi-functional capability allows the circuit to replace multiple static Write Assist circuits designed for different operating conditions, thereby reducing the overall area required while maintaining write operation reliability throughout the entire operating range.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Device complexity

If static Write Assist circuits are used, then the design can be simplified, but the circuit cannot adapt to changing operating conditions (voltage, temperature, frequency)

Engineering Contradiction:
ImproveWrite Assist circuit complexityVSAvoidadaptability to operating conditions
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent implements feedback by incorporating monitoring mechanisms that detect operating conditions (voltage, temperature, frequency) and use this information to dynamically adjust Write Assist circuit parameters. The feedback loop enables the circuit to adapt to changing operating conditions automatically, balancing the increased complexity of the adaptive mechanism against the benefits of improved versatility and performance across the operating range.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10269417B2Apparatus for adaptive write assist for memory
Publication Date: 2019.04.23 TAHOE RES LTD
  • US10269417B2 patent drawing
  • US10269417B2 patent drawing
  • US10269417B2 patent drawing

AI summary

Described is an apparatus which comprises: a memory; a first power supply node to receive a first power supply; a second power supply node coupled to the memory to provide the memory with second power supply; a circuit coupled to the first and second power supply nodes, the circuit operable to dynamically modulate droop in the second power supply by adaptively adjusting signal characteristics of a write assist pulse.