Digital Storage TRIZ Cases

A semiconductor memory device incorporates a redundancy sense amplifier system with a smaller redundancy replacement unit compared to the normal replacement unit.

A semiconductor apparatus circulates test data through internal control blocks using a shared loop to reduce hardware overhead.

Refresh controller selectively enables word lines based on redundancy cell status to prevent data loss during refresh operations.

A nanowire transistor merges with a resistive random access memory structure inside a single substrate pillar to boost cell density.

Detecting rank data widths enables the memory controller to synchronize clocks and chip selects, reducing signal drive load and improving DDR5 operation speed.

A delay code determining unit generates a final delay trim code using an internal clock to adjust timing in semiconductor memory devices.

Stacked diffusion regions and shared contact plugs in MRAM layouts reduce chip area while lowering power consumption.

A memory control method inverts external data based on cell array tendency to reduce parity bit usage.

Detects reference signal phase shifts to adjust the phase difference between data and write clock signals, ensuring accurate data recovery despite jitter.

Segmented voltage generators supply distinct write voltages to magnetoresistive elements, preventing back hopping errors and excessive current flow.

Pre-charge switches in a sense amplifier circuit minimize offset voltage, reducing read latency caused by device mismatch.

Merging MRAM and ReRAM regions on one substrate resolves integration complexity while enabling high-speed microcontroller applications.

A latch circuit uses a width adjusting mechanism to couple enable and address latches after boot-up for improved reliability.

Physical layer executes memory training and power management, reducing controller complexity.

A high voltage generation circuit uses dynamic pump switching between parallel and series modes to rapidly establish target voltage levels.

Inner and edge connection lines electrically link dummy lines to prevent disconnections from physical shocks, ensuring continuous bias voltage supply.

A semiconductor memory device uses a control signal to activate a temperature sensing unit during a power save mode.

A thermo sensor integrated into a memory module outputs temperature change signals to adjust the DRAM refresh rate dynamically.

Programmable delay circuits synchronize data signals to JEDEC standard DIMMs, resolving signal integrity issues caused by excessive latency.

A semiconductor device senses data by controlling bit line connections via voltage levels.

A capacitorless semiconductor memory cell uses a write transistor and read transistor with vertically stacked channel structures to increase storage density.

Dynamic write assist circuit modulates power supply collapse to optimize memory operations.

Transferring firing characteristics from a trained source core eliminates lengthy STDP training for identical target cores.

Dynamic voltage biasing minimizes leakage currents and disturbances to neighboring cells during read operations.

Adjusting circuit reduces detected offset voltage magnitude to converge duty ratio toward 50% and prevent erroneous data detection.

Clock tuners delay asynchronous signals to dual-port memory cells, resolving testing accuracy limits in synchronous systems.

A shared second relief information storing unit reduces chip area and transfer time for semiconductor redundancy.

Frontside and backside SRAM bit line distribution reduces routing resistance and parasitic capacitance while increasing packing density.

Adjusting N-well bias voltage compensates for threshold shifts, enabling smaller memory cell designs.

Sequential register clocking reduces power consumption by avoiding simultaneous activation of storage and filter flip flops.

Reading redundant configuration wordlines via validation logic resolves non-addressable ROMFUSE data challenges, ensuring correct operational setup.

A header circuit controls supply voltage using PMOS transistors to manage cell power levels.

Upper metal layer routing for a processing in memory chip reduces wiring congestion and latency while improving scalability.

Concurrent drift determination on disjoint memory subsets selects optimal read voltage, reducing latency and improving reliability.

A complementary dual-modular redundancy memory cell stores paired data levels in separate bitcells for internal comparison.

Magnetic random-access memory elements store binary logic values from static RAM cells, preventing data loss during power-down operations.

A configurable pseudo-dual-port memory architecture enables concurrent read and write operations through independent internal clock generation for each port.

A semiconductor memory device generates write pulses and extends their duration upon receiving a second command within a time window.

Asymmetrical memory circuit improves soft error resistance without increasing static power consumption or cell area.

A boosting word line driver applies a delayed boosted voltage to compensate for resistive drops along nano-scale memory lines.

A precharge voltage control circuit generates distinct voltage levels for bit lines and complementary bit lines to activate sense amplifiers.

A multibit MRAM cell uses a synthetic antiferromagnetic storage layer and dipolar field induction to encode multiple logic states.

Depth-wise block processing reduces memory-access overheads and energy costs by evaluating all layers for a given block before moving to the next.

Stacking spin orbit torque layers on magnetic tunneling junctions reduces chip area while lowering power consumption compared to conventional sensors.

A memory control device repeats initial data during preamble signals to establish stable signal levels before writing a series of data.

A refresh control device segments addresses to generate targeted refresh operations for specific word lines.