Semiconductor Memory Redundancy Sense Amplifier Design
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Solution Overview
Problem
Semiconductor memory devices face challenges in efficiently managing redundancy columns to maintain yield and operation speed, particularly when the page size is reduced, leading to increased redundancy column ratios and interconnect delays.
Innovation Solution
The semiconductor memory device incorporates a redundancy sense amplifier system with a smaller redundancy replacement unit compared to the normal replacement unit, allowing for efficient redundancy operations without increasing the redundancy area ratio, and employs a shift data-line replacement system to shorten local data lines and reduce interconnect delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the page size is reduced, then the memory density is improved, but the redundancy column ratio increases and interconnect delays worsen
Solution Approach 1:
The memory device is divided into multiple banks, each containing memory cell arrays and associated sense amplifiers. The redundancy sense amplifiers are selectively activated based on failure detection in specific banks, allowing localized redundancy operations without affecting the entire memory device, thus reducing interconnect delays.
Solution Approach 2:
The patent introduces a hierarchical structure with banks at one level and memory cell arrays within banks at another level. The redundancy sense amplifiers operate at the bank level, providing a dimensional organization that reduces the scope of interconnect operations and delays.
2Reliability
If the redundancy area is increased to handle more failure bits, then the yield is improved, but the operation speed decreases due to larger redundancy replacement units
Solution Approach 1:
The system dynamically selects and activates only the necessary redundancy sense amplifiers based on failure detection in specific banks. This dynamic activation allows the redundancy area to be scaled up for better yield while maintaining fast operation by engaging only the required redundancy resources rather than the entire redundancy array.
Solution Approach 2:
Each bank has its own associated sense amplifiers and can independently activate redundancy sense amplifiers when failures are detected. This local quality approach allows redundancy operations to be performed locally in affected banks rather than requiring global redundancy operations across the entire memory device, thus improving operation speed.
3Reliability
If more redundancy sense amplifiers are added to cover more failure cases, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The redundancy sense amplifiers are designed to be universally applicable across multiple banks. Each redundancy sense amplifier can replace failed sense amplifiers in different banks through selective activation, providing multi-functional capability that reduces the total number of redundancy sense amplifiers needed while maintaining comprehensive failure coverage.
Solution Approach 2:
The system includes failure detection circuitry that automatically identifies failed sense amplifiers and activates appropriate redundancy sense amplifiers without external intervention. This self-service mechanism simplifies the control logic and reduces the complexity of managing the redundancy sense amplifier system.
Data Source
AI summary
A semiconductor memory device includes: a bank including a normal area including normal columns, and a redundancy area including redundancy columns and to be replaced with a failure column of the normal area; sense amplifiers connected to the normal area; and a redundancy sense amplifier connected to the redundancy area. A normal replacement unit is formed of normal columns allocated to each of the sense amplifiers. A redundancy replacement unit is formed of redundancy columns allocated to the redundancy sense amplifier. The redundancy replacement unit is smaller than the normal replacement unit.