Processing In Memory Chip Interconnection Network Routing
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Solution Overview
Problem
Conventional memory systems face challenges in adding processing capabilities due to limitations in wiring and routing resources, leading to reduced scalability and increased energy consumption, particularly with two-dimensional processing in memory (2D PIM) systems.
Innovation Solution
The implementation of a processing in memory (PIM) chip with a memory array, logic components, and an interconnection network, where the interconnection network includes switches and interconnect wires strategically located in upper metal layers to enhance communication and processing efficiency, allowing for improved routing and reduced latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If processing capabilities are added to memory using conventional interconnection architectures, then processing functionality is enabled, but wiring and routing resources are exhausted, limiting scalability
Solution Approach 1:
The patent utilizes the vertical dimension by placing interconnection network wires in upper metal layers (e.g., metal layers 4 and 5) above the memory array, rather than confining all connections to the plane of the memory cells. This three-dimensional interconnection approach provides additional routing space and reduces congestion in conventional two-dimensional routing, thereby enabling processing capabilities without exhausting wiring resources
Solution Approach 2:
The interconnection network is segmented into multiple metal layers, with different layers serving different functions. Lower metal layers (1-3) handle memory array connections while upper metal layers (4-5) handle logic component interconnections. This segmentation allows independent optimization of routing resources for memory and processing functions, preventing resource exhaustion
2Adaptability or versatility
If complex on-chip interconnection is used to support scalability in PIM, then scalability is improved, but component and interconnect placement becomes significantly more difficult
Solution Approach 1:
By moving interconnection network wires to upper metal layers above the memory array, the patent creates additional vertical space for routing complex interconnects without increasing lateral congestion. This dimensional transition simplifies placement by providing more routing channels and reducing conflicts between memory and logic component connections
Solution Approach 2:
The interconnection network acts as an intermediary layer between memory array components and logic components. By placing this intermediary network in upper metal layers, the patent mediates the complex routing requirements, separating the placement constraints of memory cells from logic components and simplifying the overall design process
3Power
If dedicated processors and separate memories are used, then processing power is sufficient, but energy consumption during access operations is significant
Solution Approach 1:
The patent merges processing capabilities (logic components) directly with memory structures on the same chip, creating a processing-in-memory (PIM) architecture. This integration eliminates the need for separate processors and memories, reducing the energy consumed during data access operations by minimizing data movement between separate components while maintaining sufficient processing power
Data Source
AI summary
The systems and methods are configured to efficiently and effectively include processing capabilities in memory. In one embodiment, a processing in memory (PIM) chip a memory array, logic components, and an interconnection network. The memory array is configured to store information. In one exemplary implementation the memory array includes storage cells and array periphery components. The logic components can be configured to process information stored in the memory array. The interconnection network is configured to communicatively couple the logic components. The interconnection network can include interconnect wires, and a portion of the interconnect wires are located in a metal layer area that is located above the memory array.