Parallel Pseudo-Dual-Port Memory Clock Control
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Solution Overview
Problem
Pseudo-dual-port SRAM architectures face performance degradation and increased circuit area requirements due to sequential read and write operations, which are slower compared to single-port or dual-port SRAMs, and lack efficient power management.
Innovation Solution
A configurable parallel pseudo-dual-port memory architecture that enables concurrent read and write operations by independent control of internal clocks for port A and port B, allowing simultaneous access to memory banks without sequential dependency, thus reducing overall cycle time and dynamic power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If pseudo-dual-port SRAM uses sequential read and write operations to reduce circuit area and static power, then circuit area is reduced, but performance degrades and cycle time increases
Solution Approach 1:
The patent implements dynamic operation modes that allow the memory to switch between sequential and parallel operations based on control signals. The internal clock generation circuitry dynamically adjusts timing to enable parallel read-write operations when needed, resolving the contradiction between area efficiency and performance by providing adaptive operational flexibility.
Solution Approach 2:
The patent changes the timing parameters and operational mode parameters to enable parallel operations. By modifying the internal clock phases and timing relationships, the system can achieve simultaneous read and write operations, transforming the performance characteristic while maintaining the area-efficient pseudo-dual-port architecture.
2Area of stationary object
If pseudo-dual-port SRAM implements sequential operations, then circuit area is reduced, but cycle time increases by 1.8 times
Solution Approach 1:
The patent introduces dynamic timing control that adjusts the operational sequence based on mode selection signals. When parallel mode is enabled, the internal clocking mechanism dynamically reconfigures to allow overlapping read and write operations, reducing cycle time while maintaining area efficiency.
Solution Approach 2:
The patent implements preliminary clock phase generation that prepares the timing signals in advance for parallel operations. By pre-configuring the internal clock phases and timing relationships, the system can execute parallel read-write operations without the sequential delays that previously extended cycle time.
3Productivity
If pseudo-dual-port memory enables concurrent read and write operations, then performance increases, but dynamic power consumption increases
Solution Approach 1:
The patent implements self-managing clock generation circuitry that automatically adjusts internal clock phases and enables/disables clocking based on operational mode. This self-service mechanism allows the memory to achieve parallel operations when needed while automatically reducing power consumption during sequential operations, balancing performance and power efficiency.
Solution Approach 2:
The patent dynamically changes operational parameters including clock enable signals and timing phases based on mode selection. By adjusting these parameters, the system can achieve high-performance parallel operations when required while maintaining lower power consumption during standard sequential operations.
4Use of energy by stationary object
If pseudo-dual-port memory uses 6-T SRAM architecture, then static power is reduced, but performance degrades due to sequential operations
Solution Approach 1:
The patent implements dynamic operational modes in the 6-T SRAM architecture that allow switching between sequential and parallel operations. This dynamic capability enables the low-power 6-T architecture to achieve high performance when needed, resolving the contradiction between static power efficiency and performance by providing adaptive operational flexibility.
Solution Approach 2:
The patent modifies timing and control parameters to enable parallel operations in the 6-T architecture. By changing the operational mode parameters and internal clock timing, the system can achieve simultaneous read-write operations while maintaining the static power efficiency of the 6-T SRAM design.
Data Source
AI summary
A pseudo-dual-port memory (PDPM) is disclosed that includes a first memory array bank and a second memory array bank of a plurality of memory array banks. The PDPM also includes parallel pin control logic circuitry configured to perform operations including taking a clock signal, a memory enable signal for a first port, a memory enable signal for a second port, a parallel pin control signal, and address signals for the first and the second memory array banks as inputs and generating a first internal clock and a second internal clock for performing operations corresponding to the first and the second memory array banks at the first port and the second port. A total number of memory array banks may be up to eight memory array banks and each including either a six-transistors (6-T) SRAM bit-cell or an eight-transistors (8-T) SRAM bit-cell in static random access memory architecture.