SRAM N-well Bias Adjustment for Stability
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Solution Overview
Problem
Designing SRAM memory cells that are stable across operational modes, process variations, and product lifecycles is challenging due to factors like transistor threshold voltage changes caused by process variations, doping fluctuations, and radiation, leading to increased device sizes and costs.
Innovation Solution
The design involves creating SRAM memory cells with smaller gate lengths by considering local variations and adjusting the N-well bias post-fabrication to maintain stability, using a voltage booster to enhance write stability and dynamic well bias adjustments based on operational modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If longer channel lengths are used in MOSFET devices, then memory cell stability is improved, but memory cell size increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the N-well bias voltage to compensate for threshold voltage variations caused by process variations, doping fluctuations, and temperature changes. This allows the use of shorter channel lengths while maintaining memory cell stability across different operational conditions and over product lifetime.
Solution Approach 2:
The patent implements dynamics by introducing dynamic N-well bias adjustment based on operational mode (read or write) and environmental conditions. The bias voltage is modified post-fabrication to optimize transistor characteristics for specific operations, enabling smaller memory cells that maintain stability through adaptive parameter tuning rather than fixed long channel lengths.
2Area of moving object
If shorter gate lengths are used, then memory cell size is reduced, but stability across operational modes and process variations deteriorates
Solution Approach 1:
The patent uses parameter changes by adjusting the N-well bias voltage to compensate for threshold voltage variations. This dynamic parameter adjustment allows shorter gate lengths to be used while maintaining stability across read and write operations, process variations, temperature changes, and product lifetime.
Solution Approach 2:
The patent implements feedback by monitoring and adjusting N-well bias based on operational mode and observed performance characteristics. This feedback mechanism enables the system to automatically tune transistor behavior to maintain stability despite using shorter gate lengths that are more sensitive to variations.
3Reliability
If N-well bias is adjusted post-fabrication, then read and write stability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by performing N-well bias adjustment during the fabrication process or immediately after, before the device is delivered to the customer. This preliminary tuning allows stability optimization to be built into the manufacturing process itself, reducing the need for complex post-fabrication adjustment mechanisms and lowering overall device complexity.
Data Source
AI summary
Circuits, systems, and methods are disclosed for SRAM memories. An SRAM includes memory cells wherein read stability and write stability can be modified by adjusting a well bias signal operably coupled to an N-well of the memory cell. The well bias signal is generated at VDD or at a bias offset from VDD for both the read and the write operations. The memory cells may be adjusted for operation by designing the memory device to be stable relative to local parameter variations with a well bias substantially equal to VDD. The memory cells are then tested for stable read operations and stable write operations. If the write operations are unstable or the read operations are unstable, the well bias is modified and the memory cells are tested again.