Asynchronous Clock Tuners for Dual-Port Memory Testing
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Solution Overview
Problem
Conventional systems for testing dual-port memory cells transmit synchronous clock signals, which do not accurately reflect the operational behavior of these cells, limiting the effectiveness of digital circuit testing.
Innovation Solution
A system comprising a source clock and dual-port memory cells with clock tuners that delay and transmit clock signals asynchronously to each input port, allowing independent control of delay times to simulate various operational scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If synchronous clock signals are transmitted to both ports of dual-port memory cells, then the testing system is simple and easy to operate, but the testing accuracy does not reflect actual operational behavior
Solution Approach 1:
The clock signal transmission path is segmented into separate controllable paths for each port. Each port receives clock signals through independent clock tuners that can be individually controlled, allowing asynchronous operation while maintaining separate signal paths. This segmentation enables accurate simulation of real operational conditions without requiring complete system redesign.
Solution Approach 2:
The system introduces dynamic controllability to clock signal transmission by implementing clock tuners with adjustable delay parameters. The clock signals can be dynamically adjusted to different time delays for each port, enabling the system to adapt to various operational scenarios and accurately reflect the dynamic behavior of dual-port memory cells in real applications.
2Measurement precision
If asynchronous clock signals are transmitted to dual-port memory cells, then the testing accuracy reflects operational behavior, but the device complexity increases
Solution Approach 1:
The clock tuner module serves multiple functions: it can operate in synchronous mode for simple testing, asynchronous mode for accurate operational simulation, and provides adjustable delay parameters for various test scenarios. This multi-functionality allows a single system to handle both simple and complex testing requirements without requiring separate dedicated systems for each mode.
Solution Approach 2:
Clock tuners are introduced as intermediary components between the clock signal source and the dual-port memory cell ports. These intermediaries provide the necessary delay adjustment and signal conditioning, simplifying the overall control architecture while enabling asynchronous operation. The intermediaries handle the complexity of timing adjustments, making the system easier to operate despite the increased functionality.
Data Source
AI summary
Embodiments of the disclosure provide systems and methods for transmitting clock signals asynchronously to dual-port memory cells. A system according to embodiments of the disclosure may include a source clock configured to generate a clock signal, a dual-port memory cell having a first input port, and a second input port coupled to the source clock. A clock tuner coupled between the source clock and the first input port of the dual-port memory cell delays the clock signal by one of a plurality of delay times and transmits the clock signal to the first input port.