Memory Device Precharge Voltage Control for Parallel Test

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Solution Overview

Problem

Current semiconductor memory devices cannot select multiple sense amplifiers on a word line within one cycle for parallel test mode, limiting the ability to perform simultaneous testing of memory cells.

Innovation Solution

A memory device and method that utilize a precharge voltage control circuit and sense amplifier circuit to generate different precharge voltages for bit lines and complementary bit lines, allowing for voltage level changes during test write and read sensing periods to enable simultaneous testing of multiple sense amplifiers on a word line.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional single precharge voltage is applied to bit line and complementary bit line, then normal reading operation is maintained, but parallel test mode cannot be achieved

Engineering Contradiction:

Improveparallel test mode capabilityVSAvoidprecharge voltage control circuit

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The precharge voltage control circuit generates different precharge voltage levels (first precharge voltage and second precharge voltage) for the bit line and complementary bit line respectively, segmenting the voltage control to enable selective activation of sense amplifiers during test operations

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The precharge voltage control circuit dynamically adjusts voltage levels based on operation mode: during normal reading, both lines receive the same precharge voltage; during test operations, different voltage levels are applied to enable parallel testing of multiple sense amplifiers

Inventive Principle:

Principle #15Dynamics

2Productivity

If multiple sense amplifiers are selected for parallel testing, then testing efficiency is improved, but voltage control complexity increases

Engineering Contradiction:

Improvetesting efficiencyVSAvoidvoltage control circuit

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The circuit changes voltage parameters (precharge voltage levels) to control sense amplifier selection: by applying different voltage levels to bit line and complementary bit line, multiple sense amplifiers can be activated simultaneously for parallel testing, improving productivity without requiring additional control circuits

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10566034B1Memory device with control and test circuit, and method for test reading and writing using bit line precharge voltage levels

Publication Date: 2020.02.18 WINBOND ELECTRONICS CORP

AI summary

A memory device and a method for test reading and writing thereof are provided. A precharge voltage control circuit is based on the precharge reference voltage to provide a first precharge voltage and a second precharge voltage. A sense amplifier circuit is coupled between a bit line and a complementary bit line and configured to sense data of a memory cell coupled to the bit line, and also coupled to the precharge voltage control circuit to make the bit line and the complementary bit line receive the first precharge voltage and the second precharge voltage respectively, the first precharge voltage and the second precharge voltage are on the same voltage level during the precharge operation, but during a test write sensing period and a test read sensing period after the precharge operation, the voltage levels of the first precharge voltage and the second precharge voltage are different.