Semiconductor Test Loop Circulation for Pad Count Scaling

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Solution Overview

Problem

The increasing number of pads in semiconductor apparatuses for data input/output operations prolongs test time due to limited electrical coupling lines, making it difficult to efficiently test multiple semiconductor apparatuses simultaneously.

Innovation Solution

The semiconductor apparatus incorporates a test loop control unit, data input/output control blocks, and output inversion select units to latch and circulate test data through multiple data transfer paths, allowing for simultaneous testing of multiple data input/output control blocks using a single test data input pad and output pad, thereby maintaining consistent test time regardless of the number of pads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of pads for data input/output is increased to increase data input/output speed, then the data input/output capacity is improved, but the test time is prolonged

Engineering Contradiction:
Improvedata input/output speedVSAvoidtest time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The invention divides the test function into multiple data input/output control blocks (first control block, second control block, etc.), each capable of independent testing. This segmentation allows parallel testing of multiple blocks simultaneously, preventing test time from increasing proportionally with the number of pads.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention creates a universal test data circulation path that can be shared across multiple data input/output control blocks. The test data input pad, test data output pad, and circulation path serve all control blocks simultaneously, allowing one test infrastructure to handle multiple functions and blocks without requiring proportional increases in test resources.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Device complexity

If the number of lines for electrical coupling is limited, then the device complexity is reduced, but the number of semiconductor apparatuses that can be tested simultaneously is reduced

Engineering Contradiction:
Improvenumber of electrical coupling linesVSAvoidnumber of apparatuses tested simultaneously
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The invention merges the test data paths of multiple control blocks into a single shared circulation path. Test data from the test data input pad is circulated through all control blocks sequentially and collected at the test data output pad, combining multiple test functions into a unified infrastructure that requires minimal additional lines regardless of the number of control blocks.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The invention introduces a test data circulation path as an intermediary mechanism that mediates between the limited test pads and multiple control blocks. This circulation path acts as a shared resource that enables multiple blocks to be tested through a common interface, decoupling the number of test lines from the number of controllable blocks.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9336903B2Semiconductor apparatus
Publication Date: 2016.05.10 SK HYNIX INC
  • US9336903B2 patent drawing
  • US9336903B2 patent drawing
  • US9336903B2 patent drawing

AI summary

A semiconductor apparatus includes an input buffer configured to buffer data inputted through a data input/output pad; a data input control unit configured to transfer an output of the input buffer to a data input/output line in response to a write clock; a test loop control unit configured to output one of a signal of the data input/output line and test latch data in response to a test mode signal; a data output control unit configured to output an output of the test loop control unit in response to a read clock; an output inversion select unit configured to output an output signal of the data output control unit by inverting or non-inverting it; and an output buffer configured to buffer an output signal of the output inversion select unit and output a resultant signal to a node which is coupled with the data input/output pad and input buffer.