Asymmetrical Memory Circuit Soft Error Resistance

Solution Overview

Problem

Existing memory circuits face challenges in improving soft error resistance without increasing static power consumption, memory cell area, or decreasing the functional write margin.

Innovation Solution

The implementation of asymmetrical memory circuits with cross-coupled inverters, where one inverter has transistors with a larger drive current than the other, enhances soft error resistance by maintaining logic states during energetic particle strikes without significant increases in power consumption or area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If transistor sizes are increased to improve soft error resistance, then reliability is improved, but static power consumption increases and memory cell area increases

Engineering Contradiction:

Improvesoft error resistanceVSAvoidstatic power consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent applies asymmetry by making the first inverter's transistors larger than the second inverter's transistors. Specifically, the first inverter includes a first NMOS transistor and a first PMOS transistor with larger channel widths than the corresponding transistors in the second inverter. This asymmetric sizing provides enhanced soft error resistance for the first inverter while avoiding the need to increase all transistor sizes, thereby limiting the increase in static power consumption and memory cell area.

Inventive Principle:

Principle #4Asymmetry

2Reliability

If transistor sizes are increased to improve soft error resistance, then reliability is improved, but memory cell area increases

Engineering Contradiction:

Improvesoft error resistanceVSAvoidmemory cell area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent applies asymmetry by making the first inverter's transistors larger than the second inverter's transistors. Specifically, the first inverter includes a first NMOS transistor and a first PMOS transistor with larger channel widths than the corresponding transistors in the second inverter. This asymmetric sizing provides enhanced soft error resistance for the first inverter while avoiding the need to increase all transistor sizes, thereby limiting the increase in static power consumption and memory cell area.

Inventive Principle:

Principle #4Asymmetry

3Reliability

If symmetrical transistor sizing is used, then manufacturing simplicity is maintained, but soft error resistance is reduced

Engineering Contradiction:

Improvesoft error resistanceVSAvoidtransistor sizing symmetry

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies asymmetry by making the first inverter's transistors larger than the second inverter's transistors. Specifically, the first inverter includes a first NMOS transistor and a first PMOS transistor with larger channel widths than the corresponding transistors in the second inverter. This asymmetric sizing provides enhanced soft error resistance for the first inverter while avoiding the need to increase all transistor sizes, thereby limiting the increase in static power consumption and memory cell area.

Inventive Principle:

Principle #4Asymmetry

Data Source

PatentEP4517755A1Asymmetrical memory circuits and methods

Publication Date: 2025.03.05 ALTERA CORP

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AI summary

A memory circuit includes first and second inverters that are cross coupled. The first inverter is configured to provide a first drive current from a first supply line to store a first logic state in the memory circuit. The first drive current is larger than a second drive current that the second inverter is configured to provide from the first supply line to store a second logic state in the memory circuit.