Image Sensing System Register Activation Control

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Solution Overview

Problem

Existing image processing architectures consume high power due to simultaneous clocking of shift registers and flip flops in storage devices and filters during image sensing data processing.

Innovation Solution

An image sensing system with a storage device having more registers in one direction than the other, coupled with a filter and a SIPO circuit, where data is read in series from one direction and written to the filter's registers based on addresses, reducing the number of active registers during data processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If shift registers of the storage device and flip flops of the filter are clocking simultaneous on every clock pulse to shift received image sensing data, then the data processing is efficient and fast, but the power consumption becomes high

Engineering Contradiction:
Improvedata processing efficiencyVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements periodic action by enabling shift registers and flip flops in a sequential manner rather than simultaneously. The storage device processes data in periods where only its shift registers are activated, followed by periods where only the filter's flip flops are activated. This periodic activation pattern maintains data processing continuity while significantly reducing instantaneous power consumption by avoiding simultaneous clocking of all registers.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent applies segmentation by dividing the data processing task into two separate phases: a storage device processing phase and a filter processing phase. During the first phase, the storage device's shift registers are activated to transfer data to intermediate storage. During the second phase, the filter's flip flops are activated to process the stored data. This segmentation of processing stages prevents simultaneous activation of all registers, resolving the power consumption issue while maintaining processing efficiency.

Inventive Principle:
Principle #1Segmentation

2Productivity

If a large number of flip flops are clocked simultaneous on every clock pulse to handle image sensing data through filter and storage device, then the data throughput is high, but the power consumption increases significantly

Engineering Contradiction:
Improvedata throughputVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent implements periodic action by enabling shift registers and flip flops in a sequential manner rather than simultaneously. The storage device processes data in periods where only its shift registers are activated, followed by periods where only the filter's flip flops are activated. This periodic activation pattern maintains data processing continuity while significantly reducing instantaneous power consumption by avoiding simultaneous clocking of all registers.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent applies segmentation by dividing the data processing task into two separate phases: a storage device processing phase and a filter processing phase. During the first phase, the storage device's shift registers are activated to transfer data to intermediate storage. During the second phase, the filter's flip flops are activated to process the stored data. This segmentation of processing stages prevents simultaneous activation of all registers, resolving the power consumption issue while maintaining processing efficiency.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11838659B2Image sensing system and image sensing data processing method
Publication Date: 2023.12.05 PIXART IMAGING INC
  • US11838659B2 patent drawing
  • US11838659B2 patent drawing
  • US11838659B2 patent drawing

AI summary

An image sensing system comprising: a storage device, comprising at least two first registers, wherein a number of the first registers following a first direction of the storage device is larger than a number of the first registers following a second direction of the storage device; a filter, comprising at least two second registers; and an SIPO (serial in parallel out) circuit, coupled between the storage device and the filter.