SRAM Asymmetric Interconnection Frontside Backside Routing
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Solution Overview
Problem
The scaling down of integrated circuit devices leads to issues such as metal filling problems, increased routing resistance, parasitic capacitance, shorting, leakage, alignment margins, and reduced packing density, particularly in SRAM structures, due to the challenges of tighter pitch metal layers and smaller feature sizes.
Innovation Solution
The proposed solution involves an asymmetric layout for SRAM bit cells, where power lines and signal lines are distributed on both the frontside and backside of the substrate, optimizing metal routing resistance and parasitic capacitance by configuring bit lines and word lines asymmetrically to reduce coupling effects and increase spacing, thereby enhancing circuit performance and packing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If metal interconnect is continuously scaling down to less feature sizes for circuit routing density improvement, then routing density is improved, but metal filling problems occur due to barrier metal layers reducing the sizes of metal lines and metal plugs
Solution Approach 1:
The patent applies asymmetry by distributing power lines and signal lines on different sides of the substrate (frontside and backside), creating an asymmetric interconnection layout that optimizes metal routing while avoiding filling problems in tighter pitch metal layers
Solution Approach 2:
The patent moves interconnection routing to another dimension by utilizing both frontside and backside of the substrate for metal routing, effectively adding a spatial dimension to the interconnection architecture to improve routing density without compromising metal filling capability
2Quantity of substance
If device sizes are scaled down, then packing density is improved, but routing resistance increases
Solution Approach 1:
The patent reduces routing resistance by distributing signal paths across both frontside and backside of the substrate, effectively creating shorter and more optimized routing paths that compensate for the scaled-down device dimensions while maintaining high packing density
3Quantity of substance
If metal lines are placed closer together to improve routing density, then routing density is improved, but parasitic capacitance increases
Solution Approach 1:
The asymmetric distribution of power lines and signal lines on different sides of the substrate reduces parasitic capacitance by increasing spacing between coupled signal paths while maintaining high routing density through optimized metal layer utilization
4Quantity of substance
If feature sizes are reduced to improve device density, then device density is improved, but alignment margins are reduced
Solution Approach 1:
The patent segments the interconnection architecture into frontside and backside components, allowing independent optimization of each segment with appropriate design rules and manufacturing tolerances, thereby maintaining alignment margins while achieving high device density
Data Source
AI summary
A semiconductor structure includes a substrate having a frontside and a backside; a static random-access memory (SRAM) circuit having SRAM bit cells formed on the frontside of the substrate, wherein each of the SRAM bit cells including two inverters cross-coupled together, and a first and second pass gates coupled to the two inverters; a first bit-line disposed on the frontside of the substrate and connected to the first pass gate; and a second bit-line disposed on the backside of the substrate and connected to the second pass gate.