Configurable Timing Control for Memory Systems
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Solution Overview
Problem
Memory systems with delays longer than one clock cycle or non-integer number of clock cycles are not compatible with industry standards for DIMMs like UDIMM, RDIMM, or LRDIMM, leading to signal integrity issues and incompatibility.
Innovation Solution
A system and method providing a configurable timing control using a re-timer circuit with a clock generation circuit, flip-flops, and programmable delays to synchronize data signals with DIMM clocks, allowing for programmable timing adjustments to match existing DIMM standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If signal delay through CPIO or RT device is increased to accommodate longer data paths, then signal integrity is improved, but the delay becomes a significant percentage of the operating period causing timing violations
Solution Approach 1:
The patent segments the memory system into multiple components (CPIO device, RT devices, DIMM modules) with distributed re-timing functions. Each segment has its own delay compensation mechanism, allowing the overall system to maintain timing integrity across long data paths without a single point of failure or excessive cumulative delay.
Solution Approach 2:
RT devices serve as intermediary components between the CPIO device and DIMM modules. These intermediaries provide localized re-timing and delay compensation, breaking the direct long-path signal transmission into shorter segments that can be managed independently, thus maintaining signal integrity while controlling overall delay.
2Adaptability or versatility
If programmable delay circuits are added to achieve precise timing control, then compatibility with JEDEC standards is improved, but device complexity increases
Solution Approach 1:
The RT devices are designed with universal re-timing capabilities that can be configured to work with various JEDEC standard DIMM types (UDIMM, RDIMM, LRDIMM). The same basic circuit architecture serves multiple standard compliance requirements through programmable delay settings, avoiding the need for different hardware designs for each standard.
Solution Approach 2:
The patent implements dynamically programmable delay circuits that can be configured at runtime based on the specific DIMM type and timing requirements. This dynamic adaptability allows a single device design to comply with multiple JEDEC standards without requiring complex static circuit variations for each standard.
3Measurement precision
If re-timer circuits are implemented to synchronize data signals with DIMM clocks, then timing precision is improved, but the number of components and system complexity increases
Solution Approach 1:
The patent merges the re-timing function with the existing RT device architecture that is already part of the memory system. By integrating timing synchronization capabilities into components that are already present for other purposes, the patent achieves precise timing control without adding entirely separate re-timer circuits for each function.
Data Source
AI summary
A system and method for providing a configurable timing control of a memory system is provided. One system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has flip-flops, a multiplexer coupled to the flip-flops, a first control block for controlling to hold an input data within the flip-flops, and a second control block for controlling a timing of an output data from the flip-flops via the multiplexer with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface.