Capacitorless Semiconductor Memory Cell With Vertical Stacked Transistors
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing memory cell density due to the large size of capacitors in conventional one transistor to one capacitor (1T-1C) structures.
Innovation Solution
The semiconductor device incorporates a memory cell with a write transistor and a read transistor that are electrically connected, featuring a write channel structure extending perpendicular to the substrate, and a read channel layer with a read word line and bit line disposed at opposite ends.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 1T-1C structure is used, then memory cell functionality is achieved, but memory cell density is limited due to large capacitor size
Solution Approach 1:
The invention extracts and removes the capacitor component from the memory cell structure, transitioning from a 1T-1C configuration to a capacitorless 1T structure. The memory cell now uses only a single transistor with a vertically extending channel, eliminating the need for a separate capacitor while maintaining memory functionality through the transistor's off-state current characteristics.
Solution Approach 2:
The invention transitions from a planar two-dimensional layout to a three-dimensional structure by extending the channel vertically in the z-direction. The channel structure rises perpendicular to the substrate surface, allowing memory cells to be stacked in multiple layers and significantly increasing storage density within the same footprint area.
2Quantity of substance
If memory cell density is increased, then storage capacity is improved, but device footprint is reduced
Solution Approach 1:
The memory device utilizes vertical stacking in the z-direction to increase storage capacity without expanding the planar footprint. Multiple memory cell layers are stacked above each other, with each layer containing transistors with vertically extending channels, thereby achieving high density within a compact footprint.
Solution Approach 2:
The invention implements a nested structure where multiple memory cell layers are stacked vertically, with each layer containing transistors that are nested above previous layers. The bit lines and word lines are also stacked in multiple levels, creating a compact nested architecture that maximizes storage density within the available volume.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a three-dimensional stacking of transistors, increasing memory cell density without the need for capacitors, thereby enhancing storage capacity in a reduced footprint.
Implementation Method 1
the read transistor's gate dielectric layer functions as a charge storage dielectric, allowing for the storage of signal information without a traditional capacitor
Data Source
AI summary
A semiconductor device includes a memory cell including a write transistor and a read transistor that are electrically connected to each other. The write transistor includes a write bit line disposed over a substrate, a write channel structure disposed on the write bit line and extending in a direction perpendicular to a surface of the substrate on the write bit line, a write gate dielectric layer disposed on a side surface of the write channel structure, and a write word line disposed on the write gate dielectric layer. The read transistor includes a read gate electrode layer disposed on the write channel structure, a read gate dielectric layer disposed on the read gate electrode layer, a read channel layer disposed on the read gate dielectric layer, and a read word line and a read bit line that are disposed at opposite ends of the read channel layer.