Integrated Pillar ReRAM Transistor Cell Density
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Solution Overview
Problem
Current resistive random access memory (ReRAM) designs with a single transistor and single memory structure (1T1R) limit cell density and size reduction due to separate transistor and memory structure regions.
Innovation Solution
Integration of the transistor and resistive random access memory structure in a pillar protruding from the substrate, with a gate dielectric layer, electrodes, doped regions, and a metal silicide layer, allowing for a nanowire transistor electrically connected to the memory structure, enhancing cell density and simplifying manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the transistor and memory structure are disposed in different regions, then the device structure is simple and easy to manufacture, but the cell density cannot be effectively increased and the size cannot be further reduced
Solution Approach 1:
The patent merges the transistor and resistive random access memory structure into a single integrated device. The transistor is formed with the memory structure sharing common components (such as the pillar structure), allowing both functions to coexist in the same spatial region. This integration directly increases cell density while maintaining manufacturability through unified processing steps.
Solution Approach 2:
The transistor structure is nested within the same pillar region as the memory structure. The gate electrode of the transistor is positioned around the pillar, while the memory elements are formed within the pillar itself, creating a nested configuration where one structure is contained within or alongside the other, maximizing space utilization.
2Volume of moving object
If the transistor and memory structure are integrated in the same pillar, then the cell density is increased and size is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent employs preliminary patterning actions where a single pillar structure is formed first, and then both the transistor gate and memory structure components are defined from this common template. This preliminary formation of the shared pillar simplifies subsequent processing steps compared to forming separate structures independently.
Solution Approach 2:
The pillar structure serves multiple functions simultaneously: it acts as both the memory structure substrate and the transistor channel region. The gate electrode serves dual purposes as both the transistor control element and a reference electrode for the memory structure. This multi-functionality reduces the total number of components and simplifies the overall manufacturing process.
Data Source
AI summary
Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes a substrate having a pillar protruding from a surface of the substrate, a gate surrounding a part of a side surface of the pillar, a gate dielectric layer, a first electrode, a second electrode, a variable resistance layer, a first doped region and a second doped region. The gate dielectric layer is disposed between the gate and the pillar. The first electrode is disposed on a top surface of the pillar. The second electrode is disposed on the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The first doped region is disposed in the pillar below the gate and in a part of the substrate below the pillar. The second doped region is disposed in the pillar between the gate and the first electrode.