SRAM Header Circuit Voltage Control Leakage
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Solution Overview
Problem
Traditional write assist techniques for SRAM cells are associated with undesirable leakage, data corruption, and require additional supply voltage, and are difficult to control.
Innovation Solution
A header circuit is introduced that controls the supply voltage using a PMOS transistor configuration, comprising a pull-up and pull-down PMOS transistor, a passing unit, and control units to manage voltage levels, enabling write assist and power management by clamping the supply voltage at a threshold voltage below the supply voltage level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional write assist techniques are used, then write operation is facilitated, but leakage increases and data corruption occurs
Solution Approach 1:
The patent changes the voltage parameter dynamically by introducing a header circuit that adjusts the supply voltage to the SRAM cell during write operations. The circuit transitions the cell supply voltage from a first level (Vdd) to a second level (Vdd - Vth) and back, enabling write assist while controlling leakage and preventing data corruption through precise voltage timing
2Productivity
If traditional write assist techniques are used, then write operation is facilitated, but additional supply voltage is required
Solution Approach 1:
The header circuit uses the existing supply voltage Vdd and the intrinsic threshold voltage Vth of PMOS transistors to generate the required voltage levels. The circuit self-regulates by using the threshold voltage drop across the PMOS transistor to automatically produce Vdd - Vth without requiring an external additional voltage supply, reducing system complexity
3Productivity
If supply voltage is controlled to enhance write-ability, then write operation improves, but leakage may increase
Solution Approach 1:
The header circuit applies periodic voltage transitions to the SRAM cell supply, switching between Vdd and Vdd - Vth in controlled sequences. This periodic action enables write operations only when needed while maintaining higher voltage levels during non-write periods, thereby improving write-ability when required while minimizing leakage current during standby operations
Data Source
AI summary
One or more techniques or systems for controlling a supply voltage of a cell are provided herein. Additionally, one or more techniques or systems for mitigating leakage of the cell are provided. In some embodiments, a header circuit is provided, including a first pull-up p-type metal-oxide-semiconductor (PMOS) transistor including a first gate, a first source, and a first drain. Additionally, the header circuit includes a second pull-down PMOS transistor including a second gate, a second source, and a second drain. In some embodiments, the first drain of the first pull-up PMOS transistor is connected to the second source of the second pull-down PMOS transistor and a supply voltage line for one or more cells. In this manner, a pull-down PMOS is configured to control the supply voltage of the cell, thus facilitating voltage control for a write assist, for example.