ADC BIST Sliding Histogram for Low-Memory Linearity Testing
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Solution Overview
Problem
Traditional methods for testing analog-to-digital converters (ADCs) require large memory resources and complex instrumentation, leading to inefficiencies and increased chip complexity, particularly in determining differential and integral nonlinearity through histogram-based testing.
Innovation Solution
A built-in self-test (BIST) component using hardware registers and a sliding histogram technique synchronizes with an input voltage ramp to calculate differential and integral nonlinearity without traditional memory, allowing for efficient testing of ADCs by analyzing digital codes within a sliding window and incrementally updating subsets to cover all codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional memory is used to store histogram data for ADC testing, then measurement precision is improved, but device complexity and memory resource requirements increase significantly
Solution Approach 1:
The patent divides the histogram testing process into segments by implementing a sliding window that processes a subset of digital codes at a time. Instead of storing and processing all 2^N codes simultaneously in large memory, the windowed approach segments the code space into manageable portions that can be processed sequentially with minimal memory resources, thereby reducing device complexity while maintaining measurement precision.
Solution Approach 2:
The patent introduces a temporal dimension to the histogram testing process by using a sliding window that moves through the code space over time. This transforms the traditional spatial storage problem (requiring large memory to store all histogram data simultaneously) into a temporal processing problem (processing subsets sequentially), effectively reducing memory resource requirements while preserving measurement capability.
2Measurement precision
If large memory is allocated for histogram-based testing, then measurement precision is improved, but area occupied on chip increases
Solution Approach 1:
The patent applies segmentation by dividing the full code range into smaller subsets processed by a sliding window. This allows the use of small on-chip memory to store only the current window's histogram data rather than allocating large memory for the entire code space, thereby reducing chip area while maintaining DNL and INL calculation accuracy through systematic sequential processing.
Solution Approach 2:
The patent transforms the memory storage problem from a spatial challenge (requiring large static memory array occupying chip area) to a temporal challenge (processing data streams over time). The sliding window technique processes code subsets sequentially, allowing minimal memory footprint on chip while achieving complete code space coverage through time-multiplexed operation.
3Measurement precision
If HDL memories are used to implement large memory capacity, then measurement precision is improved, but writing efficiency decreases due to sequential read-write operations
Solution Approach 1:
The patent segments the histogram accumulation process into discrete windowed portions, allowing each segment to be processed and written to memory independently. This segmentation enables parallel processing of different code subsets and eliminates the need for sequential read-write operations within the same memory location, thereby improving overall write efficiency while maintaining histogram data accuracy.
Solution Approach 2:
The patent introduces temporal multiplexing to the memory access pattern, where different code subsets are processed and written to different memory locations or time slots. This transforms the inefficient sequential access pattern into a more parallel time-multiplexed access pattern, improving memory write efficiency while preserving complete histogram data for accurate DNL and INL calculations.
Data Source
AI summary
A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram technique to save space on the chip. A subset of detected digital codes are analyzed, and DNL and INL calculations are performed by a controller to determine whether any of the digital codes in the subset exceed maximum or minimum DNL and INL thresholds. New digital codes being detected by the ADC are added to the subset as lower-value digital codes are pushed out of the subset, maintaining the same number of digital codes being analyzed as the subset moves from lower codes detected during lower voltages to higher codes detected at higher voltages. A synchronizer and pointer ensure that the subset moves through the digital codes at the same rate as the analog input ramp source.