Analogue-Digital Converters TRIZ Cases

A sliding-window histogram lets ADC BIST measure DNL and INL with far less on-chip memory while staying synchronized to the input ramp.

Matched capacitors use charge exchange and equal division to avoid binary-weight matching limits and improve ADC linearity and monotonicity.

A feedback loop sums differential phase-to-digital outputs to calibrate VCO ADC mean frequency without replica VCO power, area, or mismatch.

A split-signal ADC path uses adaptive amplitude and phase matching to extend dynamic range without gain-switch glitches or calibration.

Higher-frequency offset capacitor switching cuts on-chip capacitor size while preserving wide-range, high-resolution capacitance measurement.

A dual-feedback switched-capacitor stage decouples gain from reference scaling, widening ADC input range while easing voltage headroom.

A short-circuit reset path in a differential sample-and-hold ADC cuts capacitive loading and inter-sample interference to speed conversion.

By sorting repeated conversion results and excluding extreme values, this analog input case stabilizes digital output under noise without slowing conversion.

Correct phase samples are superposed over the fundamental period to restore a faulty phase accurately without heavy memory use or external synchronization.

Alternating code sequences of different lengths in one track expand absolute angle positions while keeping decoding tables manageable.

By changing ADC sampling rates across Nyquist bands, the receiver separates aliased interference and detects DME signals over wider channels.

Error-vector analysis estimates sample clock frequency offset, enabling fractional resampling for more accurate baseband demodulation.

ADC-based digital filtering corrects magneto-resistive head asymmetry and inter-symbol interference without complex analog compensation.

A single coded ruler and camera-based interpolation deliver nanoscale absolute position measurement while reducing alignment, noise, and thermal errors.

Mode-locked laser clocking and photonic ADCs help radar sample broad-band RF signals at tens of GHz with lower EMI and phase noise.

Per-channel and M-periodic filters compensate frequency-response mismatch in time-interleaved ADCs, restoring resolution with lower filter order.

Fast and slow preamplifier gain reduction helps hearing devices prevent ADC clipping while reducing pumping and switching noise.

Variable weighting crossfades digitized signal paths to avoid clipping artifacts while preserving dynamic range with low-resolution converters.

Multiple sampling and reversed-polarity integration improve CMOS image sensor sensitivity, noise suppression, and dynamic range.

A digital timing reference synchronizes distributed MRI receiver clocks, enabling coil-side ADCs with less wiring, lower EMI, and cleaner signals.

Multiple sample-and-hold paths capture current and voltage at exact PWM trigger times before shared ADC conversion.

A galvanically isolated analog input switch and ADC break ground loops and impedance coupling, improving multi-channel measurement accuracy.

A delay-chain time interpolator adds fine timing to single-ramp ADC channels, boosting resolution without longer conversion time or extra power.

Variable charge injection matched to detector current keeps image-sensor ADC scanning linear and unblocked across a wider light range.

Automatic latency measurement and offset calculation synchronize chained ADCs and DACs without manual path tuning or power-hungry delay circuits.

Analog-to-digital converter uses an alternating current source to monitor signal amplitude for connection integrity.

A multiplexer coupled to a control circuit configures input signals into single-ended or differential modes via a unified register.

Dual nonvolatile storage units save prior calibration settings to restore correct operation after erroneous rewrites.

A voltage control circuit uses a controller and adjustment circuit to stabilize power supply voltage.

An electronic control device varies microcomputer power supply voltage using a discrete resistor and A/D conversion, eliminating costly EEPROM components.

Offset correction circuit divides input voltage to detect ADC errors and adjust reference levels.

Concatenated distortion correction terms stored in replica memories swap with primary units to maintain operational continuity.