Converter Chain Synchronization Using Latency Measurement Offsets
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Solution Overview
Problem
Existing methods for synchronizing multiple analog-to-digital or digital-to-analog converters are complex, require significant adjustments to electrical paths, consume excessive power, or necessitate manual user intervention, leading to performance degradation and instability due to jitter and temperature variations.
Innovation Solution
A method for synchronizing converters that involves chaining them together, using internal synchronization signals with automatic latency measurement and offset calculation, eliminating the need for manual adjustments and ensuring deterministic alignment without user intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog delay components are used to realign digital-to-analog converter output signals, then synchronization is achieved, but power consumption increases significantly and adjustment becomes difficult
Solution Approach 1:
The patent replaces analog delay components (mechanical/electrical system) with a digital method using latency measurement and offset calculation. The control unit determines synchronization offsets by measuring signal propagation delays through digital timing measurements, then applies these offsets to align converter outputs without requiring power-intensive analog delay circuits.
2Reliability
If electrical path lengths are adjusted to synchronize converters within the same clock period, then synchronization is achieved, but physical constraints are imposed and sampling clock performance degrades
Solution Approach 1:
The patent replaces physical path length adjustment (mechanical system) with a digital measurement and compensation approach. Instead of physically adjusting trace lengths to achieve synchronization, the system measures the actual propagation delays through digital timing and calculates appropriate offset values, eliminating the need for complex physical adjustments and their associated constraints.
3Reliability
If frame alignment with significant memory is used for serial interfaces, then data synchronization is achieved, but memory requirements increase and precision is insufficient
Solution Approach 1:
The patent extracts the essential synchronization information (propagation delay measurements) from the data stream and uses only this critical information for offset calculation. Instead of buffering entire frames with significant memory requirements, the system measures timing relationships and applies minimal offset corrections, dramatically reducing memory needs while maintaining alignment precision.
4Adaptability or versatility
If active components are added to the clock signal path for synchronization, then converter interoperability is achieved, but temperature stability deteriorates
Solution Approach 1:
The patent replaces active clock path components (electrical system) with a digital measurement and software-based offset application approach. The system measures propagation delays through digital timing and applies offset corrections in the digital domain, eliminating temperature-sensitive active components from the clock signal path and thereby improving temperature stability while maintaining interoperability.
5Measurement precision
If manual observation and measurement are required during the learning phase, then propagation delays can be determined, but time loss occurs and user intervention is necessary
Solution Approach 1:
The patent implements self-service by enabling the control unit to automatically measure propagation delays and calculate synchronization offsets without requiring manual user intervention. The system performs the entire synchronization setup process autonomously through digital timing measurements and automated offset application, eliminating both time loss and the need for user observation and measurement.
Data Source
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AI summary
The invention relates to a method for synchronising a plurality of analogue-to-digital or digital-to-analogue converters (CONV_k), the converters (CONV_k) all being connected to a control unit (UC), as well as to a clock (CLK) having a predefined clock period (Tclk), the converters also being progressively chained together so as to form a chain of converters, each converter (CONV_k) generating an internal synchronisation signal (internal_sync_k) configured to provide a time reference for the transmission of the data via the converter (CONV_k). The method ensures the converters are synchronised using a procedure for training and configuring the converters. The method makes it possible to overcome any line distance constraint on the synchronisation signal.