Multi-Clock Capacitive-to-Digital Converter for Wide-Range Sensing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional wide-range capacitive-to-digital converters require large and costly on-chip offset, reference, and integrator capacitors, making them impractical for certain implementations.
Innovation Solution
A charge balancing capacitive-to-digital converter employing a multi-clocking and multi-referencing approach, where the switching frequency of the second clock signal is twice or more than the first, reducing the capacitance requirements of the offset, reference, or integrator capacitors, and utilizing trimmable capacitors and variable reference levels to support a wide range of sensor capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional wide-range capacitive-to-digital converters are designed to cover a wide capacitance range, then the measurement range is improved, but the required on-chip offset, reference, and integrator capacitors become large and costly
Solution Approach 1:
The patent implements dynamic capacitor switching where capacitors are alternately connected to different nodes based on clock signals. The offset capacitor and reference capacitor are switched between the first and second input nodes of the integrator, allowing the same physical capacitors to serve multiple functions and effectively reducing the total capacitance required for wide-range measurement
Solution Approach 2:
The patent employs periodic switching of capacitors using clock signals (first clock signal for sensor capacitor, second clock signal for offset and reference capacitors). This periodic action allows capacitors to be reused in different configurations over time, enabling wide measurement range without requiring permanently large capacitor values
2Quantity of substance
If the switching frequency of the second clock signal is increased to twice or more than the first clock signal, then the capacitance requirements are reduced, but the circuit complexity increases
Solution Approach 1:
The offset capacitor and reference capacitor serve multiple functions by being switched to different nodes. These capacitors participate in both offset cancellation and reference voltage generation across different clock cycles, allowing reduced capacitance values while maintaining functionality. The multi-clocking scheme enables these capacitors to fulfill multiple roles that would otherwise require separate dedicated capacitors
Solution Approach 2:
The patent changes the switching frequency parameter of the second clock signal to be twice or more than the first clock signal. This parameter change allows the capacitors to switch states more frequently, effectively reducing the required capacitance values while the systematic clocking approach manages the increased switching complexity
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
A capacitive-to-digital converter is provided which includes: sensor, offset and reference capacitors, an integrator circuit and a demodulation circuit. The sensor capacitor is switched according to a first clock and the offset capacitor according to a second clock, which has a higher switching frequency. The reference capacitor is switched according to a return signal from the converter's output. The integrator circuit includes an integrator capacitor, and has first and second nodes, with the sensor, offset and reference capacitors each being switched to the first and second nodes based on the respective first clock, second clock or return signal. The demodulation circuit receives and converts output of the integrator circuit into a digital output. The higher frequency clocking of the offset capacitor allows for a reduction in capacitance of the offset, reference or integrator capacitor, and the multiclocking of the converter allows for use of a multireferencing to the sensor capacitor.