Image Sensor Readout Circuit With Multi-Sampling Noise Cancellation
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Solution Overview
Problem
Existing CMOS image sensors face challenges in achieving both high sensitivity and low noise while maintaining a wide dynamic range, as simple amplification methods fail to ensure both performance metrics simultaneously.
Innovation Solution
The proposed A/D converter and readout circuit implement multiple-times sampling and integration of signals with reversed polarity, utilizing operational amplifiers and capacitors to enhance the signal-to-noise ratio by multiplying the signal component by the number of integrations and the noise component by the square root of the number of integrations, thereby improving the S/N ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If simple amplification is used to reduce noise, then noise reduction is achieved, but dynamic range is limited
Solution Approach 1:
The patent segments the amplification process into multiple discrete gain stages (e.g., gain=1, gain=2, gain=4, gain=8) that can be selectively activated. This allows the system to divide the overall dynamic range into multiple segments, each handled by an appropriate gain level, thereby achieving both noise reduction at low signals and full dynamic range coverage at high signals.
Solution Approach 2:
The patent implements dynamic gain switching where the amplification factor is not fixed but changes based on the input signal level. The system dynamically selects among multiple gain levels (1, 2, 4, 8) to match the current signal conditions, enabling adaptive noise reduction while preserving the full dynamic range capability across varying illumination conditions.
2Measurement precision
If high-gain amplification is used to achieve low noise, then sensitivity is improved, but the ability to handle wide dynamic range is compromised
Solution Approach 1:
The patent employs dynamic gain control where the amplification factor is adjusted based on the input signal level. Multiple gain levels (1, 2, 4, 8) are available and selectively activated to match the current signal conditions, enabling the system to achieve high sensitivity when needed while maintaining the ability to handle the full dynamic range.
Solution Approach 2:
The patent changes the amplification parameter (gain factor) based on the input signal characteristics. By having multiple discrete gain levels and selecting the appropriate one for each signal level, the system optimizes sensitivity for weak signals while avoiding saturation for strong signals, thus achieving both high sensitivity and wide dynamic range coverage.
3Device complexity
If fixed gain amplification is used, then circuit simplicity is maintained, but both high sensitivity and wide dynamic range cannot be achieved simultaneously
Solution Approach 1:
The patent segments the amplification function into multiple parallel pathways, each with a fixed gain level (1, 2, 4, 8). This segmentation allows the use of simple fixed-gain amplifier circuits while achieving complex adaptive performance through selective combination of the segmented gain levels, thus maintaining circuit simplicity while expanding performance range.
Solution Approach 2:
The patent creates a multi-functional amplification system where a single readout circuit can perform multiple gain levels (1, 2, 4, 8) through selective activation of different amplification pathways. This universal design allows the same hardware to adapt to different signal conditions, achieving both high sensitivity and wide dynamic range without requiring entirely separate circuits for each function.
Data Source
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AI summary
An A/D converter 11 performs multiple-times sampling on a first signal S1 in a first period T1 while performing multiple-times sampling on a second signal S2 in a second period T2. An A/D converter circuit 17 provides a digital signal in response to a signal from an output 15b of a gain stage 15 in the second period T2. The digital signal may have a value "1" or a value "0". The A/D converter circuit 17 includes a circuit 18 providing a signal SA/DM corresponding to the number of times the value "1" appears. A switch 24 operates in response to a clock signal ϕs and is used to sample a signal from a pixel 2a. In a first capacitor circuit 27, a switch 29 and a capacitor 31 are connected to an inverting input 23a and a non-inverting output 23b, respectively. The switch 29 operates in response to a clock signal ϕ3 and is used for integration in the capacitor 31.