Single-Ramp ADC Time Interpolation for Higher Resolution
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Solution Overview
Problem
Single ramp type Analog to Digital Converters (ADCs) face limitations in conversion time, which increases with the number of bits, making them unsuitable for high-resolution applications, especially in fields like nuclear science where fast and accurate conversion is critical.
Innovation Solution
Incorporating a delay-chain time interpolator in each channel of the ADC, which operates within a clock period to provide fine conversion data, combining it with coarse conversion data for enhanced resolution without increasing power consumption or slowing down the ramp generator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of bits for digital data is increased to improve dynamic range and resolution, then measurement precision is improved, but conversion time increases
Solution Approach 1:
The patent segments the conversion time measurement into two parts: coarse conversion data from the digital counter and fine conversion data from the delay-chain time interpolator. This segmentation allows the system to achieve high resolution without proportionally increasing the total conversion time, as the interpolator provides sub-clock-period precision without requiring a full additional clock period for each bit.
Solution Approach 2:
The delay-chain time interpolator acts as an intermediary between the coarse digital counter output and the final high-resolution conversion result. It takes the comparator trigger signal and the clock signal as inputs, and produces fine conversion data that interpolates time within a clock period, thereby resolving the time measurement with higher precision without extending the overall conversion cycle.
2Measurement precision
If a delay-chain time interpolator is added to provide fine conversion data, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The delay-chain time interpolator is designed to be a shared resource across multiple channels in multi-channel applications. The interpolator receives trigger signals from comparators of different channels and processes them through the same delay chain structure, allowing one interpolator to serve multiple functions and channels, thereby reducing the overall complexity compared to having separate interpolators for each channel.
Solution Approach 2:
The patent implements servo-control to dynamically adjust the delay parameters of the delay-chain interpolator. By controlling the delay in each delay cell to equal an integer fraction of a clock period, the system optimizes the interpolator's performance and linearity, ensuring high measurement precision while maintaining manageable device complexity through adaptive parameter adjustment.
3Productivity
If the conversion time is reduced for high-speed applications, then productivity is improved, but measurement precision may deteriorate
Solution Approach 1:
The patent utilizes periodic clock signals to drive both the digital counter and the delay-chain time interpolator. The clock provides a regular, periodic timing reference that enables the system to achieve high conversion rates while maintaining precision. The periodic nature of the clock allows for synchronized operation of all components and enables the interpolator to accurately measure time intervals within each clock period.
Solution Approach 2:
The delay-chain time interpolator performs preliminary time interpolation on the comparator trigger signal before the final conversion result is produced. By pre-processing the trigger signal through the delay chain and synchronizer, the system prepares fine conversion data in advance, allowing the final conversion to be completed quickly without sacrificing precision. This preliminary action enables high conversion rates while maintaining accurate time measurement.
Data Source
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AI summary
The invention provides an analog-to-digital converter (ADC) of the single ramp type, comprising a ramp generator (101), a clock (102), a digital counter (103) timed by the clock (102), and at least one channel (101,..., 10i, , 10n) for data processing, the or each channel comprising a comparator (201,..., 20i,..., 20n) having an input connected to the ramp generator (101) and the output of which causes for each conversion cycle the storage of the current counter value as a coarse conversion data. According to the present invention, the or each channel (101,..., 10i,..., 10n) further comprises a delay-chain time interpolator (401,..., 40i,..., 40n, 501,..., 50i,..., 50n) responsive to the output of the comparator and to the clock (102), for interpolating time within a clock period from the triggering time of the comparator, said interpolator delivering a time-interpolation output signal as a fine conversion data which is combined to the coarse conversion data for each conversion cycle. Application to an increased resolution without excess power consumption or increased conversion period.