Time-Interleaved ADC Calibration for Clock Skew Under Weak Signals
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Solution Overview
Problem
Existing analog-to-digital converter (ADC) devices face challenges in calibration due to gain, offset, and timing errors, especially when input signals are weak, leading to incorrect convergence of phase errors between channels.
Innovation Solution
A time-interleaved ADC device with a calibration circuit and controlling circuit that generates adjustment signals to reduce clock skew by analyzing time difference information and selectively performing error operations based on control signals, ensuring accurate calibration of quantized outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If calibration is performed using prior art technologies, then gain error, offset error, and timing error can be corrected, but the calibration is easily affected when the input signal is weak, leading to incorrect phase error convergence
Solution Approach 1:
The patent applies preliminary action by performing offset calibration before gain calibration and timing error correction. The offset calibration circuit first removes offset errors from all channels, providing a clean baseline for subsequent calibration steps. This sequential approach ensures that each calibration operation builds on the previous one, preventing error propagation that would occur if calibration were attempted on weak signals without this preparatory step.
Solution Approach 2:
The patent segments the calibration process into distinct functional blocks: offset calibration circuit, gain calibration circuit, and timing error correction circuit. Each segment handles a specific type of error independently. The offset calibration circuit processes offset errors, the gain calibration circuit processes gain errors, and the timing error correction circuit processes timing errors. This segmentation allows each circuit to be optimized for its specific function and prevents interference between different calibration operations, especially important when dealing with weak input signals.
2Productivity
If time-interleaved ADC structure is used to increase sampling rate, then productivity is improved, but clock skew between channels causes timing errors that degrade measurement precision
Solution Approach 1:
The patent implements feedback through the timing error correction circuit that receives quantized outputs from all ADC channels, analyzes timing differences, and generates correction signals. The circuit calculates timing errors by comparing arrival times of signals from different channels and feeds back adjustment signals to synchronize the channels. This closed-loop feedback mechanism continuously compensates for clock skew, allowing the time-interleaved structure to maintain high sampling rates while correcting timing inaccuracies.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting timing parameters of individual ADC channels based on measured skew. The timing error correction circuit modifies the sampling timing or phase of clock signals for each channel to compensate for differences. By changing the timing parameter (phase or delay) of each channel adaptively, the system maintains synchronized operation despite inherent clock skew in the time-interleaved architecture, thus preserving measurement precision while achieving high productivity.
Data Source
AI summary
An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit and a controlling circuit. The ADC circuits are configured to generate first quantized outputs according to clock signals. The calibration circuit is configured to perform at least one error operation according to the first quantized outputs to generate second quantized outputs, and is configured to analyze time difference information of the clock signals according to the second quantized outputs to generate adjustment signals. The controlling circuit is configured to analyze the first quantized outputs to generate at least one control signal to the calibration circuit, wherein the at least one control signal is configured to control the calibration circuit to selectively perform the at least one error operation and selectively analyze the time difference information of the clock signals.