Analogue/Digital Conversion Calibration/Testing TRIZ Cases

A DAC injects correction current at an intermediate node to set precise reference voltage without gain-stage noise, offset, or drift.

Multi-stage delay-to-digital calibration sets zero-crossing and over-range thresholds to improve TD ADC SQNR and high-speed output.

Calibrates time-domain ADC delay thresholds with comparator and trim feedback to improve accuracy without larger SoC overhead.

An internal self-running clock and timeout check keep SAR ADC conversion stable despite external clock frequency deviations.

Parallel ADC paths compare an input and its complement with XOR logic to catch invalid conversions during normal operation without software overhead.

Progressive correlation with different bit widths and iteration counts calibrates interleaved ADC timing while cutting skew distortion, power, and time.

One comparator is recalibrated off-line while neighboring values infer its output, keeping ADC operation continuous with lower circuit size and power.

Calibrated delay timing after each DAC bit flip helps a SAR ADC avoid comparator errors and maintain accurate, efficient conversion.

Direct RF sampling with dual-pipe ADCs reconstructs wideband spectra without mixers, reducing instrument complexity, power, and weight.

A frequency-modulated calibration sweep captures TI-ADC mismatch across wide bands faster, reducing switching, circuit complexity, and cost.

Comparator feedback and trim circuitry calibrate time-domain ADC delay thresholds to improve accuracy while reducing settling time and mismatch errors.

Internal reference-voltage integration and timing let this A/D converter calibrate offset and unit voltages without external instruments.

Compensation codes and gain control correct ADC and amplifier DC offsets, improving receiver linearity and signal conversion accuracy.

A switched capacitor circuit derives ADC error voltage directly from stored samples, cutting buffer amplifier errors, charge loss, and conversion time.

Adjustable trim circuits calibrate multi-stage delay-domain ADC residue stages to correct nonlinearity across the full input range.

A shared current-source switching scheme links LSB and MSB stages to cut switch count while preserving monotonicity and linearity.

A shared-capacitor SAR ADC cuts PAM-6 receiver comparator count from seven to three, reducing area and power while preserving conversion capability.

Digital equalization in a time-interleaved DAC removes image frequencies and corrects sub-DAC mismatch with less silicon area.

Uses task latency periods in dual-channel engine control units to detect faulty components earlier and support faster isolation and maintenance.

An asynchronous SAR and flash ADC split MSB and LSB conversion to raise speed, preserve 12-bit resolution, and limit power use.

A/B resistance segmentation with tunable headers and footers matches DAC wireline impedance while cutting area, power, and mismatch.

One comparator is taken offline and its output inferred from neighboring comparators, enabling continuous ADC calibration with less power and switching complexity.

Joint calibration of capacitor arrays and channel timing in a time-interleaved SAR ADC improves accuracy, convergence speed, and real-time operation.

Subtractive dithering and digital mismatch correction reduce inter-segment distortion in segmented DACs and improve SNDR in deep back-off.

Bandgap-generated internal reference voltages let an ADC self-calibrate without external reference pins, improving measurement consistency.

Correlation values from adjacent ADC samples drive clock phase correction, reducing time skew distortion in time-interleaved conversion.

Redundant DAC elements and LSB-based self-calibration correct split-capacitor mismatch and parasitics to improve SAR ADC linearity.

A re-laid current source array cuts gradient error and parasitic capacitance while helping DACs suppress even-order nonlinearity.

Segmented current slopes approximate exponential LED drive current without lookup tables, reducing circuit complexity and over-current risk.

Sequential tuning of thermometer segment strength cuts systematic DAC INL by comparing differential output with a dithered ideal reference.

Separate trim circuits calibrate residue-stage delay comparators across voltage ranges to improve ADC linearity at high speed.

Measures consecutive DAC output pulses to correct clock-phase skew and duty-cycle distortion, improving high-speed EVM.

Stored comparison results let SAR ADC calibration finish before overwrite, preserving accurate digital output at high operating frequencies.

Multiple TDL sectors with dedicated latching clocks improve timestamp precision and reduce noise through calibrated thermometer encoding.

Bandgap-generated internal voltages let an ADC self-calibrate without external reference pins, improving measurement accuracy and consistency.

NCO-based phase compensation corrects timing skew in interleaved ADCs, suppressing spurs with low power and minimal hardware overhead.

Segmenting ADC input codes into index and coarse values shrinks lookup-table memory while preserving high-speed linearity correction.

Detector circuitry tunes channel clock delays and amplifier gains to correct timing skew and gain mismatch in time-interleaved ADCs.

Simple code-domain addition and subtraction correct SAR ADC capacitor mismatch, improving linearity and calibration accuracy with lower circuit complexity.

Segmenting ADC calibration codes into coarse and index values corrects GSPS non-linearity while cutting lookup memory and power.

Calibration circuitry tests clock phase sequences and selects the best sampling order to improve interleaved ADC accuracy without extra area or power.

Quantizer offset differences separate gain error from offset error, enabling concurrent circuit-block calibration with lower noise and power penalties.

Ramp timing calibration derives scaling factors to correct multi-range ADC mismatches, preventing missing codes and non-monotonic output.

Asynchronous resets and shared pre-amplification help a level-crossing ADC cut power, limit leakage error, and preserve SNDR.

Dual residue outputs enable pipeline ADC calibration that corrects amplifier gain drift and noise buildup while preserving fast conversion.

Iterative timing self-calibration adjusts SAR ADC global delay to handle PVT drift, preserve settling time, and avoid bit truncation.

Selective error operations and timing analysis help a time-interleaved ADC correct clock skew and avoid false phase convergence under weak signals.

Ping-pong error DACs calibrate current sources through a current mirror to stop error buildup and improve DAC conversion accuracy.

Built-in sine-wave and DAC test circuitry enables parallel ADC dynamic testing without external testers, cutting cost and improving throughput.

Iterative global-delay self-calibration lets an asynchronous SAR ADC maintain settling time under PVT variation without bit truncation.

Bypass-switched current-steering cells correct common-mode errors in resistor ladder DACs, improving calibration and static linearity.

A ramp-based trip-point test followed by static or slow-slope code monitoring speeds ADC linearity checks and supports calibration drift control.

Multi-bit delay-cell calibration adapts TDC resolution to PVT and DCO frequency changes, preserving timing coverage and noise performance.

PN code injection lets a pipelined ADC estimate capacitor mismatch and inter-stage gain errors without interrupting conversion, improving SFDR and SNDR.