Current Source Array Layout for Low-Error DAC Matching

Solution Overview

Problem

Current digital-to-analog converters (DACs) face challenges in mitigating both systematic mismatch and parasitic capacitance, leading to performance degradation, and even-order nonlinearity introduces a DC offset that cannot be eliminated through static DC compensation.

Innovation Solution

A current source array with uniquely numbered current sources arranged in rows and columns, combined with a DAC circuit featuring lateral shielding and automatic calibration, to reduce area, minimize parasitic capacitance, and suppress even-order nonlinearity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If current sources are arranged in a conventional layout to increase chip integration level, then the chip area is reduced, but the systematic mismatch becomes more severe and parasitic capacitance increases

Engineering Contradiction:

Improvechip areaVSAvoidsystematic mismatch

Core Design Contradiction:

Area of stationary objectVSManufacturing precision

Solution Approach 1:

The current source array is segmented into multiple groups, with each group containing current sources of the same current source number. These groups are distributed across different locations in the array, allowing the systematic mismatch to be averaged out while maintaining high integration level.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from a conventional one-dimensional or simple two-dimensional layout to a structured two-dimensional grid layout where current sources are arranged in rows and columns. This dimensional organization enables systematic mismatch mitigation through spatial distribution while controlling parasitic capacitance through controlled grouping.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If current sources are arranged in a conventional layout to increase chip integration level, then the chip area is reduced, but the parasitic capacitance increases substantially

Engineering Contradiction:

Improvechip areaVSAvoidparasitic capacitance

Core Design Contradiction:

Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The current source array is segmented into multiple groups, with each group containing current sources of the same current source number. These groups are distributed across different locations in the array, allowing the systematic mismatch to be averaged out while maintaining high integration level.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from a conventional one-dimensional or simple two-dimensional layout to a structured two-dimensional grid layout where current sources are arranged in rows and columns. This dimensional organization enables systematic mismatch mitigation through spatial distribution while controlling parasitic capacitance through controlled grouping.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Measurement precision

If static DC compensation is used during calibration, then the DC offset can be compensated, but the even-order nonlinearity cannot be fundamentally suppressed

Engineering Contradiction:

ImproveDC offset compensationVSAvoideven-order nonlinearity suppression

Core Design Contradiction:

Measurement precisionVSReliability

Solution Approach 1:

The patent applies preliminary anti-action by designing the current source array layout to preemptively suppress even-order nonlinearity before the DAC operation. Through the specific arrangement where current sources of the same number are distributed across multiple groups, the even-order nonlinearity is fundamentally reduced at the source, making static DC compensation unnecessary for this particular distortion component.

Inventive Principle:

Principle #9Preliminary anti-action

Data Source

PatentUS20250253859A1Current source array, digital-to-analog converter and signal chain chip

Publication Date: 2025.08.07 HANGZHOU GEO-CHIP TECH CO LTD

AI summary

Disclosed are a current source array, a digital-to-analog converter, and a signal chain chip, the current source array comprising current sources each uniquely numbered and laid out in rows and columns, wherein in the first column, current source numbers for current source units in the first half of rows are determined from the row numbers, and the numbers of rows and columns, and current source numbers for current source units in the second half of rows are determined from the row numbers, the numbers of rows and columns, and current source numbers determined for the first half of rows; and current source numbers for current source units in each subsequent column are determined from current source numbers determined for the previous column, thereby forming an overall layout of current source array. Through the above re-layout of current sources, the overall area can be reduced, thus decreasing the gradient error.