Multi-Stage Delay-to-Digital Calibration for ADC Linearity
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Solution Overview
Problem
Pipeline ADCs are limited in operating speed, making them unsuitable for high-frequency applications like RF-sampling receivers, and existing delay-domain ADCs face non-linearities in time-to-digital conversion that affect accuracy.
Innovation Solution
A multi-stage delay-domain ADC with independent calibration of delay comparators and logic functions in each residue stage, using separate trim circuits to adjust response times based on input voltage ranges, ensuring accurate conversion across the full input voltage range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a pipeline ADC architecture is used, then the conversion process is structured in manageable stages, but the operating speed is limited and unsuitable for high-frequency applications
Solution Approach 1:
The patent replaces the traditional voltage-domain processing with a time-domain processing system. The voltage-to-delay converter transforms the input voltage into a time delay, which is then processed by the TDC. This substitution of domain (from voltage to time) enables higher operating speeds suitable for RF-sampling receivers while maintaining the staged conversion approach.
2Productivity
If a delay-domain ADC is used to achieve high speed operation, then operating speed increases, but non-linearities in time-to-digital conversion reduce accuracy
Solution Approach 1:
The patent segments the conversion process into distinct functional blocks: voltage-to-delay converter, delay-to-digital converter, and calibration circuits. Each residue stage is independently calibratable, allowing precise adjustment of individual components to compensate for non-linearities while maintaining high-speed operation.
Solution Approach 2:
The patent employs calibration circuits that adjust timing parameters and delay values to compensate for non-linearities. By dynamically changing the delay parameters in the TDC based on calibration data, the system maintains high measurement precision across the full input voltage range while operating at high speeds.
3Measurement precision
If independent calibration of each residue stage is implemented, then accuracy across full input voltage range is improved, but device complexity increases
Solution Approach 1:
The patent performs calibration operations in advance during manufacturing or initialization. The calibration circuits measure and store correction values for each residue stage beforehand, which are then applied during normal operation. This preliminary calibration action ensures high accuracy without requiring complex real-time calibration mechanisms.
Solution Approach 2:
The calibration system is designed to be self-contained within each residue stage, with each stage having its own trim circuits and calibration logic. This modular self-service approach allows independent calibration of each stage without requiring complex external calibration equipment or centralized control, thereby managing complexity while achieving high precision.
Data Source
AI summary
A delay-domain analog-to-digital converter including a voltage-to-delay circuit and a time-to-digital converter circuit, and a method of calibrating the same. The voltage-to-delay circuit generates a delay signal based on applied calibration voltage, and the delay signal is applied to a first residue stage configured to generate a sign bit and a residue delay signal. The residue delay signal is applied to an input of a successive residue stage, which is configured to generate a sign bit and provide a residue delay signal to inputs of a next successive residue stage. First and second trim circuits are provided in a delay comparator of one of the successive residue stages, and configured to adjust a first response of the residue stage for a calibration voltage in a first range, and to adjust a second response of the residue stage for a calibration voltage in a second range.