Hybrid SAR-Flash ADC Architecture for High-Speed 12-Bit Conversion
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Solution Overview
Problem
Existing analog-to-digital converters face challenges in achieving high-speed operation, high resolution, and low power consumption, particularly in applications like digital TVs and digital cameras, where uninterrupted image reproduction is critical.
Innovation Solution
The proposed analog-to-digital converter integrates a Successive Approximation Register (SAR) conversion unit and a flash conversion unit, operating asynchronously, with an amplification unit and a calibration circuit, to generate high-resolution digital signals while minimizing power consumption. This is achieved through the use of internal and external clock signals, sampling clock signals, and complementary signals to optimize bit data determination and error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional analog-to-digital converter is used, then it can convert analog signals to digital signals, but it cannot operate at high speed with high resolution and low power consumption simultaneously
Solution Approach 1:
The converter is divided into two independent conversion units: a first conversion unit (SAR-based) that processes MSBs and a second conversion unit (flash-based) that processes LSBs. Each unit operates independently with its own clock signal, allowing high-speed flash conversion for LSBs while maintaining high resolution through the combined 12-bit output.
2Measurement precision
If a conventional analog-to-digital converter is used, then it can convert analog signals to digital signals, but it consumes excessive power
Solution Approach 1:
The power consumption is segmented and distributed across two conversion units. The first unit (SAR) consumes less power and handles MSBs, while the second unit (flash) consumes more power but handles only LSBs. This segmentation allows the system to achieve high resolution (12-bit) while controlling overall power consumption by not requiring a single high-power unit to handle all bits.
Solution Approach 2:
The converter uses dynamic clock signal generation where the flash clock signal is generated only when needed for LSB conversion. The clock signals are dynamically controlled based on the conversion stage, allowing the system to reduce power consumption by activating high-power components only when necessary.
3Productivity
If a conventional analog-to-digital converter is used, then it can convert analog signals to digital signals, but it cannot be installed in a smaller area
Solution Approach 1:
The converter architecture segments the conversion function into two specialized units, each optimized for its specific function. The first unit handles MSB conversion with simpler circuitry, while the second unit handles LSB conversion with flash architecture. This segmentation allows for more efficient space utilization on the chip compared to a single unified converter design.
Data Source
AI summary
An analog-to-digital converter of one embodiment in the present disclosure may comprise a first conversion unit generating an internal clock signal, generating a first digital code and a residual signal by converting an input signal in a successive approximation register (SAR) method in response to the internal clock signal and generating a flash clock signal in response to an external clock signal, a second conversion unit generating a second digital code by converting the residual signal in a flash method in response to the flash clock signal, and an output circuit generating an output digital signal in response to the first digital code and the second digital code.