Segmented Tapped Delay Line TDC for Precise Timestamp Capture
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Solution Overview
Problem
Existing Time to Digital Converters (TDCs) face challenges in achieving high precision and accuracy due to limitations in tap delay line (TDL) design, noise, and variability in clock and signal propagation delays.
Innovation Solution
The proposed solution involves a high precision TDC architecture that utilizes multiple tapped delay lines (TDLs) with dedicated latching clocks, snapshot registers, and a processor to generate accurate thermometer readings, which are then encoded and processed to produce timestamps with enhanced precision and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple TDLs with dedicated latching clocks are used, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The TDL is divided into multiple sectors, each sector being latched by a dedicated latching clock. This segmentation allows parallel processing of time measurements across different sectors, improving precision while managing complexity through modular organization. Each sector operates independently with its own latching clock, enabling simultaneous capture of multiple time events.
Solution Approach 2:
The patent introduces multiple dimensions of time measurement by using multiple TDLs with different latching clocks. Instead of a single sequential measurement approach, the system creates a multi-dimensional measurement space where time events can be captured from multiple clock references simultaneously, thereby improving precision through dimensional expansion.
2Measurement precision
If multiple TDLs with different latching clocks are used, then accuracy is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs calibration techniques that dynamically adjust delay parameters for each TDL sector. By measuring and compensating for manufacturing variations in delay times, the system achieves high accuracy despite inherent manufacturing tolerances. The calibration process modifies delay parameters to account for process variations, thereby decoupling accuracy from strict manufacturing precision requirements.
3Measurement precision
If advanced encoding methods are used, then noise reduction is improved, but processing time increases
Solution Approach 1:
The patent implements preliminary calibration and encoding setup before actual time measurement operations. By pre-configuring the encoding parameters and calibration data during manufacturing or initialization, the system reduces the processing burden during runtime. This preliminary action allows the measurement process to focus on noise reduction without significant processing time penalties.
Data Source
AI summary
A time to digital converter (TDC) comprising a tapped delay line (TDL) having two or more sectors, each sector of the two or more sectors having a dedicated or a shared latching clock, or two or more TDLs each having at least one sector, wherein each TDL of the two or more TDLs includes a dedicated latching clock for each sector, and a snapshot register (TDLSecS) configured to latch the sector on its respective latching clock to generate a thermometer reading.