SAR ADC Capacitor Array Calibration for Mismatch Correction

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Solution Overview

Problem

Capacitor mismatch in capacitor array type successive approximation register analog-to-digital converters (SAR ADCs) leads to increased circuit complexity, power consumption, and difficulty in improving sampling rate, while traditional calibration methods require non-binary weights, increasing redundancy and calculation complexity.

Innovation Solution

A calibration method that arranges capacitors of bits from low to high with binary weight proportions, allowing for weight calibration based on traditional binary weights, thereby reducing circuit and calculation complexity by performing simple addition and subtraction on the original output code.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If capacitor array size is increased to improve resolution and linearity, then measurement precision is improved, but device complexity and area increase exponentially

Engineering Contradiction:
Improveresolution and linearityVSAvoidcapacitor array complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent changes the weight proportion parameter from traditional binary (2^n) to non-binary with redundancy (e.g., 3^n or other redundant schemes). This allows the capacitor array to represent weights with redundancy, enabling error correction for capacitor mismatch while controlling the number of capacitors. The redundant weighting scheme transforms the parameter space to achieve both high precision and manageable complexity.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If capacitor matching degree is improved to meet linearity requirements, then measurement precision is improved, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
ImprovelinearityVSAvoidcapacitor matching difficulty
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

The patent converts the harmful effect of capacitor mismatch into a beneficial calibration mechanism. By using non-binary redundant weighting, the system can represent the same weight value through multiple capacitor combinations. This redundancy allows the calibration process to identify and correct mismatch errors, transforming the manufacturing variability (harm) into an opportunity for post-fabrication correction (benefit).

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent performs preliminary calibration measurements to determine actual capacitor weights before normal operation. By measuring the actual weight values of capacitors and storing calibration data in advance, the system prepares correction factors that will be applied during normal conversion. This preliminary action separates the manufacturing variability from the operational performance.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If traditional binary capacitor array is used to reduce circuit complexity, then device complexity is reduced, but measurement precision deteriorates due to capacitor mismatch

Engineering Contradiction:
Improvecircuit complexityVSAvoidlinearity
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent changes the fundamental weighting parameter from binary to non-binary redundant weighting. This parameter change allows the system to use a manageable number of capacitors (controlling complexity) while the redundant representation enables error correction (maintaining precision). The non-binary weights provide multiple paths to represent the same value, allowing mismatch compensation without increasing capacitor count exponentially.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12224763B2Calibration method of capacitor array type successive approximation register analog-to-digital converter
Publication Date: 2025.02.11 SHEN AN MICRO CO LTD
  • US12224763B2 patent drawing
  • US12224763B2 patent drawing
  • US12224763B2 patent drawing

AI summary

Disclosed is a calibration method of a capacitor array type successive approximation register analog-to-digital converter, comprising: obtaining an actual weight value of capacitors of a target bit and an error code between the actual weight value and an ideal weight value of the capacitors of the target bit; calibrating an output code of the SAR ADC to be calibrated with the error code by corresponding addition or subtraction to obtain a final calibrated output code. The calibration method breaks through the requirement that non-binary weights must meet the redundancy, and can realize a weight calibration in a traditional binary ADC and a digital calibration by simple addition and subtraction on the basis of the original code obtained by an analog-to-digital conversion, thus effectively avoiding the error problem in the traditional technology, increasing the calibration precision and accuracy, reducing the circuit complexity and calculation complexity caused by the non-binary weights calibration.