Asynchronous SAR ADC Timing Self-Calibration for PVT Drift
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Solution Overview
Problem
High-resolution SAR ADCs face accuracy issues due to process, voltage, and temperature variations, which require frequent recalibration, increasing system cost and complexity, and result in errors from capacitive DACs due to variations in time delay or conversion time.
Innovation Solution
An asynchronous SAR ADC with iterative timing self-calibration that adjusts the global delay of bit-conversion circuits to ensure conversion time meets a target time, using a feedback loop and control logic to minimize differences between target and actual conversion times, allowing for adaptive calibration based on historical references and environmental changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the time delay or conversion time in the feedback loop is increased to ensure sufficient settling time for high-resolution conversion, then measurement precision is improved, but productivity decreases because the conversion period becomes excessively long and may truncate bits
Solution Approach 1:
The patent applies dynamics by making the time delay parameter adjustable rather than fixed. The system dynamically adapts the time delay based on operating conditions (temperature, process variations, voltage) to optimize the balance between settling time and conversion speed. The delay can be modified through calibration procedures and environmental compensation to maintain optimal performance across different operating points.
Solution Approach 2:
The patent changes the time delay parameter to resolve the contradiction. By adjusting the time delay parameter based on calibration data and environmental conditions, the system optimizes the settling time for accurate conversion while preventing excessive delay that would truncate bits. This parameter adjustment allows the system to adapt to PVT variations and maintain both precision and productivity.
2Manufacturing precision
If production trimming is performed on capacitors to reduce errors from capacitive DAC variations, then manufacturing precision is improved, but device complexity increases due to the additional trimming process and components
Solution Approach 1:
The patent uses feedback by measuring the actual conversion results and using this information to adjust the time delay parameter. The system incorporates a calibration mechanism that observes conversion outcomes and modifies the delay to compensate for hardware variations. This feedback-based approach replaces complex physical trimming with a software-controlled parameter adjustment, reducing manufacturing complexity while maintaining precision.
Solution Approach 2:
The system performs self-calibration by automatically adjusting its own time delay parameter based on observed performance. Rather than requiring external trimming processes or additional calibration components, the ADC self-corrects for variations by modifying its operational parameters. This self-service approach reduces device complexity while achieving the desired manufacturing precision.
3Reliability
If frequent recalibration is performed to compensate for PVT variations, then reliability is improved, but loss of time increases due to recalibration overhead, and device complexity increases
Solution Approach 1:
The patent implements periodic calibration at predetermined intervals or under specific triggering conditions rather than continuous or frequent recalibration. The system monitors environmental conditions and performs calibration only when necessary (e.g., when temperature changes exceed a threshold or after a certain number of conversions). This periodic approach maintains reliability by compensating for PVT variations while minimizing time loss and operational disruption.
4Ease of operation
If the conversion time is set to a fixed value to simplify control, then ease of operation is improved, but adaptability decreases because the system cannot compensate for environmental changes
Solution Approach 1:
The patent transitions from a static fixed conversion time to a dynamic adjustable parameter. The conversion time (time delay) can be modified based on environmental conditions, process variations, and calibration results. This dynamic approach maintains ease of operation through automated control while significantly improving adaptability to changing conditions. The system handles the complexity of adaptation automatically, keeping the user interface simple while enabling environmental compensation.
Data Source
AI summary
An analog-to-digital converter (ADC) is described. This ADC includes a conversion circuit with multiple bit-conversion circuits. During operation, the ADC may receive an input signal. Then, the conversion circuit may asynchronously perform successive-approximation-register (SAR) analog-to-digital conversion of the input signal using the bit-conversion circuits, where the bit-conversion circuits to provide a quantized representation of the input signal. For example, the bit-conversion circuits may asynchronously and sequentially perform the SAR analog-to-digital conversion to determine different bits in the quantized representation of the input signal. Moreover, the ADC may selectively perform self-calibration of a global delay of the bit-conversions circuits. Note that the timing self-calibration may be iterative and subject to a constraint that a maximum conversion time is less than a target conversion time.