Time-Domain ADC Calibration for Accurate Delay Thresholds
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing analog-to-digital converters (ADCs) face limitations in power efficiency and accuracy due to reliance on voltage domain comparisons and time domain converter circuitry that requires complex calibration methods, leading to inaccuracies and increased system-on-chip size.
Innovation Solution
A method and apparatus for calibrating ADCs using a time domain comparison with reference comparator circuitry, involving first and second instances of voltage-to-delay circuitry, time domain converter circuitry, and trim circuitry to adjust delay duration thresholds through offset, shift, and mismatch corrections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If voltage domain comparisons are used in ADCs, then the conversion process is simplified, but power efficiency deteriorates and conversion time increases
Solution Approach 1:
The patent replaces voltage domain comparisons with time domain comparisons. Instead of comparing voltages directly (voltage domain), the system converts voltages to time delays using voltage-to-delay circuitry, then compares the time delays. This substitution fundamentally changes the domain of operation from voltage to time, achieving better power efficiency and faster conversion while maintaining the comparison functionality.
Solution Approach 2:
The patent changes the fundamental parameter being compared from voltage to time delay. By using voltage-to-delay circuitry to convert input voltages into proportional time delays, and reference voltages into reference time delays, the system operates in the time domain instead of voltage domain. This parameter transformation enables more efficient operation with reduced power consumption and faster conversion times.
2Productivity
If time domain converter circuitry is used, then conversion speed improves, but manufacturing precision of delay duration thresholds deteriorates
Solution Approach 1:
The patent implements a calibration system with feedback that measures the actual delay duration thresholds and adjusts them to match ideal values. The trim circuitry receives feedback about timing differences between parallel comparator paths and automatically adjusts the delay duration thresholds to compensate for manufacturing variations. This closed-loop feedback mechanism ensures high precision despite process variations.
Solution Approach 2:
The patent performs calibration of the time domain converter before normal operation. The trim circuitry pre-adjusts the delay duration thresholds to account for manufacturing variations before the ADC is used for actual conversions. This preliminary calibration action ensures that the converter operates with high precision from the start, compensating for any manufacturing imperfections in the delay elements.
3Measurement precision
If calibration circuitry is added to improve precision, then measurement precision improves, but device complexity increases
Solution Approach 1:
The patent merges the calibration functionality with the existing converter structure by using the same voltage-to-delay circuitry, comparators, and logic elements for both normal conversion and calibration operations. The trim circuitry integrates with the existing parallel comparator paths, adjusting delay thresholds in-situ without requiring separate calibration hardware. This merging approach improves precision while minimizing additional complexity.
Solution Approach 2:
The patent designs the voltage-to-delay circuitry and comparator structure to serve dual purposes: performing normal analog-to-digital conversion and enabling calibration operations. The same circuit elements are used for both conversion and threshold calibration, making the system multi-functional. This universality allows precision improvement through calibration without proportionally increasing device complexity.
4Measurement precision
If multiple comparator circuits are used for calibration, then measurement precision improves, but area of the circuit increases
Solution Approach 1:
The patent segments the calibration function into multiple parallel comparator paths that share common resources. Instead of using completely separate comparator circuits for calibration, the system divides the calibration task across multiple paths that each use a portion of the available circuitry. This segmentation allows high-precision timing measurements while distributing the area requirement across shared components rather than duplicating full comparator circuits.
Solution Approach 2:
The patent uses copies of the main comparator circuit structure for calibration purposes, but these copies share significant resources with the primary conversion path. The calibration comparators use the same basic architecture and many of the same physical components (delay elements, logic circuits) as the main converters, creating a resource-efficient copy that provides the necessary measurement precision without proportionally increasing total area.
Data Source
AI summary
An example apparatus includes: first voltage-to-delay circuitry having an output; second voltage-to-delay circuitry having an output; time domain converter circuitry having a first input, a trim input, and an output, the first input of the time domain converter circuitry coupled to the first voltage-to-delay circuitry; comparator circuitry having a first input, a second input, and an output, the first input of the comparator circuitry coupled to the output of the first voltage-to-delay circuitry and the first input of the time domain converter circuitry, the second input of the comparator circuitry coupled to the output of the second voltage-to-delay circuitry; and trim circuitry having a first input, a second input, and an output, the first input of the trim circuitry coupled to the output of the time domain converter circuitry, the second input of the trim circuitry coupled to the output of the comparator circuitry.