SAR ADC Calibration Using Redundant DAC Elements
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Solution Overview
Problem
High-resolution Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) face accuracy limitations due to device mismatch, parasitic elements, and noise, which compromise differential and integral non-linearity, particularly in split-capacitor DACs.
Innovation Solution
A self-calibration method using redundancy is employed to improve the accuracy of SAR ADCs by adjusting input-dependent voltages and incorporating redundant bits to relax settling time and comparator accuracy requirements, allowing for calibration without altering existing components, thus maintaining ideal capacitor sizes and reducing gain errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a split-capacitor DAC is used to reduce area and increase speed, then device matching and parasitic elements deteriorate, but area and speed are improved
Solution Approach 1:
The patent applies preliminary calibration action to compensate for the poor device matching caused by split-capacitor DAC. The calibration circuit measures and stores correction values for each capacitor before normal operation, allowing the system to pre-compensate for manufacturing variations and parasitic effects, thereby maintaining high precision without requiring larger capacitor sizes
2Area of stationary object
If scaling capacitors are used in split-capacitor DAC, then area is reduced, but device matching and parasitic elements worsen
Solution Approach 1:
The calibration system performs self-service by automatically measuring and compensating for the parasitic elements introduced by scaling capacitors. The calibration circuit independently characterizes each capacitor's actual value including parasitic effects, and the calibration data is used to correct conversions without requiring external intervention or larger capacitor designs
3Measurement precision
If redundancy is added for calibration, then device complexity increases, but measurement precision is improved
Solution Approach 1:
The calibration circuit is designed with multi-functionality to reduce overall device complexity. The same calibration circuitry and redundant capacitors are used for both calibration operations and normal conversion operations, eliminating the need for separate dedicated calibration components and reducing the net increase in device complexity
4Manufacturing precision
If capacitor sizes are increased to improve matching, then manufacturing precision is improved, but area increases
Solution Approach 1:
The patent changes the operational parameters of the capacitor array by introducing calibration data that dynamically adjusts the effective capacitor values. Instead of physically increasing capacitor sizes to improve matching, the system changes the electrical parameters through calibration corrections, allowing ideal capacitor sizing to be maintained while achieving high precision
Data Source
AI summary
An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) and a comparator having a first input coupled to receive an output voltage of the DAC, a second input, and a comparison output. The ADC also includes successive-approximation-register (SAR) circuitry having an input to receive the comparison output, and an output to provide an uncalibrated digital value. The DAC includes a Most Significant Bits (MSBs) sub-DAC including a set of MSB DAC elements and a Least Significant Bits (LSBs) sub-DAC including a set of LSB DAC elements. The ADC also includes calibration circuitry which receives the uncalibrated digital value and applies one or more calibration values to the uncalibrated digital value to obtain a calibrated digital value. The calibration circuitry obtains a calibration value for each MSB DAC element using the set of LSB DAC elements, the termination element, and at least one of the one or more redundant DAC elements.