Time-Domain ADC Over-Range Calibration for Higher SQNR
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing time-domain (TD) ADCs face limitations in signal-to-quantization-noise ratio (SQNR) due to non-linear voltage threshold spacing and non-linear gain, which affects accuracy and efficiency.
Innovation Solution
A time-domain ADC with a multi-stage architecture and calibration circuitry that calibrates delay-to-digital stages using zero-crossing and over-range calibrations to set thresholds relative to a reference voltage, improving SQNR and gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional time-domain ADC stages are used with non-linear voltage threshold spacing, then device complexity is reduced, but measurement precision deteriorates due to limited SQNR
Solution Approach 1:
The ADC is divided into multiple stages, each handling a specific portion of the input signal range. The first stage processes signals within a normal range with standard threshold spacing, while subsequent stages handle over-range signals with adjusted threshold spacing. This segmentation allows each stage to be optimized for its specific function, improving overall SQNR without requiring complete redesign of the entire ADC system.
Solution Approach 2:
Different stages of the ADC are assigned different threshold spacing characteristics tailored to their specific operational requirements. The first stage uses non-linear threshold spacing optimized for small-signal accuracy, while over-range stages use linear or differently-spaced thresholds optimized for large-signal handling. This local optimization of threshold characteristics improves measurement precision across the full dynamic range without uniformly increasing complexity throughout the entire system.
2Measurement precision
If gain is increased for small input signals to improve accuracy, then measurement precision improves, but device complexity increases due to non-linear gain requirements
Solution Approach 1:
The gain control is segmented into different stages, with the first stage providing high gain for small-signal accuracy and subsequent stages providing unity or reduced gain for large-signal handling. This segmentation eliminates the need for a single complex non-linear gain control mechanism, as each stage has a simplified, fixed gain characteristic appropriate for its operational range.
Solution Approach 2:
Instead of using a single stage with variable non-linear gain to handle all input ranges, the invention inverts the approach by using multiple stages with fixed gain characteristics. The first stage is designed with high fixed gain for small signals, and over-range stages are designed with unity gain, eliminating the complexity of dynamic gain adjustment while maintaining accuracy.
3Measurement precision
If multiple ADC stages are used in series to improve accuracy, then measurement precision improves, but device complexity increases due to gain limitations
Solution Approach 1:
Each stage in the multi-stage configuration is designed with local optimization for its specific operational range. The first stage is optimized for small-signal detection with high gain and non-linear threshold spacing, while over-range stages are optimized for large-signal handling with unity gain and linear threshold spacing. This local optimization allows multiple stages to work together effectively without the complexity of coordinating non-linear gain across all stages.
Data Source
AI summary
An analog-to-digital converter (ADC) includes: a time-domain ADC core; and a calibration circuit. The time-domain ADC core includes: a first delay-to-digital stage having a terminal; a second delay-to-digital stage having a terminal; a third delay-to-digital stage having a terminal. The calibration circuitry is coupled to the terminal of the first delay-to-digital stage, the terminal of the second delay-to-digital stage, and the terminal of the third delay-to-digital stage of stages. The calibration circuitry is configured to calibrate the first delay-to-digital stage, the second delay-to-digital stage, and the third delay-to-digital stage based on a zero-crossing calibration and an over-range calibration. The over-range calibration sets a maximum threshold and a minimum threshold for the time-domain ADC relative to a reference voltage.