SAR ADC Self-Running Clock for Timing Violation Detection
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Solution Overview
Problem
Existing successive approximation register A/D converters (SARADCs) face issues with timing violations due to frequency deviations in the external clock, leading to potential failures in A/D conversion, especially in high-resolution applications.
Innovation Solution
The SARADC employs a self-running clock generated asynchronously to the external clock, using a delay loop to ensure timely completion of A/D conversion, with an abnormal state detection mechanism that checks for completion within a defined time limit, allowing for robust operation even with frequency deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the SARADC uses an external clock for A/D conversion, then the conversion process is synchronized with external systems, but timing violations occur due to frequency deviations in the external clock
Solution Approach 1:
The patent combines the external clock signal with an internal delay loop to generate a self-running clock. The delay loop is configured to divide the external clock frequency by a predetermined value (e.g., 2^N where N is the resolution), creating an internal clock that is synchronized with the external clock but adjusted for timing requirements. This merging approach allows the SARADC to maintain synchronization with external systems while ensuring adequate time for each conversion cycle, thereby resolving the contradiction between conversion reliability and conversion time.
Solution Approach 2:
The patent implements preliminary action by pre-configuring the delay loop with a predetermined division ratio before A/D conversion begins. The delay loop is designed to automatically generate the appropriate number of clock cycles required for N-bit conversion (2^N cycles) based on the external clock input. This preliminary setup ensures that the conversion process has sufficient time allocated without requiring real-time adjustments, thus preventing timing violations while maintaining reliable conversion.
2Measurement precision
If the SARADC increases resolution to improve precision, then measurement accuracy improves, but the conversion time increases due to more comparison cycles required
Solution Approach 1:
The patent applies dynamics by making the clock generation adaptive to the resolution requirement. The delay loop is designed to dynamically adjust the number of clock cycles based on the resolution bit N, automatically generating 2^N cycles for N-bit conversion. This dynamic approach ensures that higher resolution conversions receive proportionally more time resources, maintaining measurement precision without unnecessary time overhead for lower resolution conversions. The system adapts the conversion time to match the actual precision requirements.
3Reliability
If the SARADC uses a self-running clock generated from external clock, then timing violations are prevented, but the system becomes independent of external clock frequency variations
Solution Approach 1:
The patent introduces the delay loop as an intermediary between the external clock and the A/D conversion process. The delay loop acts as a frequency divider that transforms the external clock signal into a self-running clock with a predetermined frequency relationship (e.g., external clock frequency divided by 2^N). This intermediary mechanism allows the system to maintain a stable, predictable timing relationship independent of external clock frequency variations, while still being triggered and synchronized by the external clock. The intermediary absorbs frequency variations, providing operational stability without sacrificing the ability to respond to external clock inputs.
Data Source
AI summary
A capacitive array D/A converter samples an input voltage, and outputs a signal that corresponds to the input voltage IN and a threshold voltage based on control data. A comparison circuit receives an output of the capacitive D/A converter and performs comparison processing according to a comparison clock. A clock generating circuit generates a successive approximation clock. A logic circuit supplies the comparison clock to the comparison circuit based on the successive approximation clock. When a predetermined second number of cycles of the successive approximation clock are detected before a predetermined number of cycles of an external clock are detected from the start of A/D conversion, the logic circuit judges that operation is normal. Otherwise, the logic circuit judges that an abnormal state has occurred.