ADC Complementary Signal Validation for Run-Time Error Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for monitoring ADC performance are resource-intensive, often requiring software or hardware testing that complicates system development and can render the IP block unavailable, and may be costly due to the need for diverse ADC architectures.
Innovation Solution
A system utilizing parallel processing paths with a primary and secondary ADC that convert an analog input signal and its complement, allowing for continuous, software-transparent run-time self-testing through bit-level validation using XOR operations, generating error statistics without processor involvement, and accommodating dynamic reference voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional testing methods using diverse ADC architectures are used, then ADC performance monitoring reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent segments the ADC functionality into two identical parallel paths, each processing a complementary version of the input signal (Vref - Vin). This segmentation allows independent validation of each path while using the same hardware architecture, resolving the contradiction by achieving reliability through functional division rather than architectural diversity.
Solution Approach 2:
The patent creates a digital copy of the ADC output and its complement, then validates them against each other using XOR logic. This copying approach enables self-validation without requiring diverse architectures, reducing device complexity while maintaining monitoring reliability.
2Ease of operation
If software-based testing is used, then system development complexity increases, but if hardware state machine testing is used, then the IP block becomes unavailable during testing
Solution Approach 1:
The patent enables continuous validation by processing complementary signals through identical parallel ADC paths simultaneously. The validation occurs continuously during normal operation without interrupting the IP block, maintaining ease of operation while eliminating availability loss through self-validating architecture.
Solution Approach 2:
The ADC system performs self-validation by comparing its own complementary outputs through XOR logic. This self-service mechanism eliminates the need for external software or state machine testing, ensuring continuous operation without IP block unavailability while maintaining ease of operation.
3Measurement precision
If diverse ADC architectures are used for testing, then measurement accuracy is improved, but manufacturing cost increases
Solution Approach 1:
The patent uses identical ADC architectures in parallel, processing homogeneous hardware that is easier to manufacture. The measurement precision is maintained through complementary signal processing and XOR validation rather than architectural diversity, reducing manufacturing cost while preserving measurement accuracy.
Solution Approach 2:
Instead of using diverse architectures to achieve validation, the patent inverts the approach by using identical architectures processing inverted/complementary signals (Vref - Vin). This inversion allows validation through signal complementarity rather than architectural diversity, maintaining measurement precision while reducing manufacturing cost.
Data Source
AI summary
A system includes an analog-to-digital converter (ADC) circuitry to convert an analog input signal to a first digital output signal, and convert a complement of the analog input signal to a second digital output signal, wherein the complement of the analog input signal comprises a difference between a reference voltage and the analog input signal, and error detection circuitry to identify an invalid conversion of the analog input signal based on the first digital output signal and the second digital output signal.