TDC Delay-Cell Calibration for PVT-Stable Timing Resolution
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Solution Overview
Problem
Conventional time-to-digital converters (TDCs) face limitations in delay resolution at low voltage, low temperature, or slow corners due to degraded inverter performance, restricting their ability to achieve optimal delay resolution and noise performance, especially in digital synthesizers where quantization noise is dominant.
Innovation Solution
The proposed solution involves a TDC circuit with multi-bit delay cells, counters, and decision logic circuits that dynamically adjust delay resolution based on process, voltage, and temperature (PVT) changes and input frequency, using a calibration method to ensure the total delay time covers at least one DCO period, thereby optimizing noise performance and insensitivity to environmental variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a maximum period of DCO clock is selected to ensure correct timing conversion, then the total delay time across all delay cells is larger than one DCO period, but the finest delay resolution is fixed and limited by the maximum period of DCO clock where the delay time is still much larger than one DCO period as DCO frequency increases several times
Solution Approach 1:
The delay cells are divided into multiple groups, with each group containing a specific number of delay elements. The calibration process selectively enables or disables entire groups of delay cells based on the measured total delay time, allowing the system to achieve both sufficient total delay (for reliability) and fine delay resolution (for precision) by adjusting which groups are active.
Solution Approach 2:
The system dynamically adjusts the delay resolution by calibrating which groups of delay cells are enabled based on the actual DCO frequency and total delay time. This dynamic configuration allows the TDC to adapt to varying operating conditions, maintaining optimal delay resolution while ensuring the total delay remains larger than one DCO period for correct timing conversion.
2Device complexity
If conventional TDC is used with coarse or fine resolution, then the circuit structure is simple, but the delay resolution is worse at low voltage, low temperature, or slow corner due to degraded inverter performance
Solution Approach 1:
The system performs a calibration process before normal TDC operation to determine the appropriate groups of delay cells to enable. This preliminary action accounts for PVT variations and ensures that the selected delay cell configuration provides sufficient total delay time, thereby guaranteeing accurate delay resolution across different operating conditions without requiring a complex circuit structure.
Solution Approach 2:
The calibration process measures the total delay time and adjusts the enabled delay cell groups based on the measured parameter. By changing which delay cell groups are active based on the total delay time parameter, the system compensates for degraded inverter performance at low voltage, low temperature, or slow corners, maintaining accurate delay resolution without increasing circuit complexity.
3Ease of operation
If delay resolution is fixed, then the circuit operation is simple, but the TDC performance is sensitive to environmental variations such as PVT changes and input frequency changes
Solution Approach 1:
The system incorporates a feedback mechanism where the total delay time is measured and used to determine which groups of delay cells should be enabled. This feedback loop allows the TDC to automatically adapt to environmental variations such as PVT changes and input frequency changes, maintaining accurate delay resolution without requiring complex real-time adjustment circuits during normal operation.
Solution Approach 2:
The calibration process is performed in advance to determine the appropriate delay cell configuration for current operating conditions. This preliminary action stores the calibration results that can be used during normal TDC operation, providing adaptability to environmental variations while keeping the circuit operation simple during actual timing measurements.
Data Source
AI summary
Apparatus, circuits and methods for calibrating time to digital converters (TDCs) are disclosed herein. In some embodiments, a circuit for calibrating a TDC is disclosed. The circuit includes a multi-bit delay circuit, a counter, and a register. The multi-bit delay circuit is configured for delaying a clock signal by a total delay time. The counter is configured for counting rising edges of the clock signal within the total delay time to generate a counted output. The register is configured for controlling the total delay time of the multi-bit delay circuit based on the counted output.