Level-Crossing ADC Reset Scheme for Low-Power SNDR Stability
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Solution Overview
Problem
Conventional analog-to-digital converters in wireless sensor nodes face challenges in minimizing power consumption, especially for low-frequency signals, due to increased area requirements and leakage-induced errors, which affect signal-to-noise-and-distortion ratio (SNDR) and power consumption.
Innovation Solution
A system and method for analog-to-digital signal conversion using a level-crossing based sampling circuit with additional asynchronous resets, a capacitive charge transfer digital-to-analog converter, and shared pre-amplification to reduce comparator offset requirements and capacitive area, eliminating the need for on-board oscillators and minimizing hold time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If level-crossing sampling is used to reduce power consumption, then power consumption decreases, but signal-to-noise-and-distortion ratio (SNDR) deteriorates due to comparator offset
Solution Approach 1:
The patent creates a replica of the DAC with identical capacitor structure but without the hold requirement, using it to generate a stable reference signal for level-crossing detection. This copy allows the main DAC to use smaller capacitors while the replica maintains accuracy for comparison purposes.
Solution Approach 2:
The patent introduces an intermediary reference signal generated by the replica DAC that mediates between the input signal and the level-crossing comparators. This intermediary provides stable reference levels that are not affected by leakage, thereby improving SNDR while maintaining low power operation.
2Duration of action of stationary object
If larger capacitors are used in DAC to meet long hold time for low frequency signals, then hold time improves, but area increases
Solution Approach 1:
The patent segments the DAC functionality into two separate units: the main DAC for power-efficient conversion and a replica DAC for generating stable reference signals. This segmentation allows each unit to be optimized independently, with smaller capacitors in the main DAC reducing area while the replica handles the hold time requirement.
Solution Approach 2:
The patent creates a replica of the DAC with identical capacitor structure but without the hold requirement, using it to generate a stable reference signal for level-crossing detection. This copy allows the main DAC to use smaller capacitors while the replica maintains accuracy for comparison purposes.
3Measurement precision
If additional reset signals are added to reset DAC between samples, then leakage-induced error decreases, but device complexity increases
Solution Approach 1:
The patent creates a replica of the DAC with identical capacitor structure but without the hold requirement, using it to generate a stable reference signal for level-crossing detection. This copy allows the main DAC to use smaller capacitors while the replica maintains accuracy for comparison purposes.
4Device complexity
If conventional ADC architecture is used, then implementation is simple, but power consumption increases for low frequency signals
Solution Approach 1:
The patent creates a replica of the DAC with identical capacitor structure but without the hold requirement, using it to generate a stable reference signal for level-crossing detection. This copy allows the main DAC to use smaller capacitors while the replica maintains accuracy for comparison purposes.
Solution Approach 2:
The patent implements level-crossing sampling where conversion occurs periodically only when the signal crosses predefined thresholds, rather than continuously. This periodic action significantly reduces power consumption for low-frequency signals while maintaining measurement accuracy through the replica DAC reference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, minimizes the requirement for larger capacitors, and enhances SNDR by providing additional resets and shared pre-amplification, effectively addressing the limitations of conventional ADCs in wireless sensor nodes.
Implementation Method 1
a capacitive charge transfer digital-to-analog converter
Implementation Method 2
an amplifier configured to amplify an error signal
Implementation Method 3
a first comparator configured to compare the error signal with respect to a first reference level, and a second comparator configured to compare the error signal with respect to a second reference level
Data Source
AI summary
Example embodiments relate to systems and methods for analog-to-digital signal conversion. One embodiment includes a system for analog-to-digital signal conversion. The system includes an analog input signal. The system also includes a digital-to-analog converter configured to generate a reference signal. Further, the system includes an amplifier configured to amplify an error signal that includes a difference between the analog input signal and the reference signal. Additionally, the system includes a level-crossing based sampling circuit that includes a first comparator configured to compare the error signal with respect to a first reference level, and a second comparator configured to compare the error signal with respect to a second reference level, thereby generating event-based reset signals corresponding to a plurality of sampling instances in order to reset the digital-to-analog converter. Yet further, the system includes a trigger circuit configured to generate reset signals asynchronous to the event-based reset signals.