Multi-Stage Delay-to-Digital Calibration for ADC Nonlinearity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Pipeline ADCs are limited in operating speed, making them unsuitable for high-frequency applications like RF-sampling receivers, and existing delay-domain ADCs face non-linearities in time-to-digital conversion that affect accuracy over the full input voltage range.
Innovation Solution
A calibrated analog-to-digital converter with a voltage-to-delay circuit and multiple residue stages, incorporating a time-domain comparator and adjustable trim circuits to compensate for non-linearities, ensuring accurate conversion across the input voltage range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pipeline ADC architecture is used, then manufacturing precision is improved, but operating speed deteriorates
Solution Approach 1:
The patent replaces the traditional voltage-domain pipeline processing with a time-domain processing system. The voltage-to-delay converter transforms the input voltage into a time delay, which is then processed by TDC stages. This substitution of the conversion domain (from voltage to time) enables high-speed operation while maintaining conversion accuracy, as time-domain processing avoids the speed limitations of traditional voltage-domain pipeline stages.
2Speed
If delay-domain ADC is used to improve operating speed, then speed is improved, but measurement precision deteriorates due to non-linearities
Solution Approach 1:
The patent implements a feedback mechanism where the digital output from the TDC is fed back to the voltage-to-delay converter. This feedback loop allows the system to compensate for non-linearities in the time-to-digital conversion process. The V2D converter uses this feedback information to adjust its conversion characteristics, thereby correcting measurement errors and improving overall conversion accuracy while maintaining high-speed operation.
Solution Approach 2:
The patent dynamically adjusts conversion parameters through the feedback mechanism. The voltage-to-delay converter modifies its conversion characteristics based on the feedback from the TDC output, changing parameters such as delay values and conversion timing to compensate for non-linearities. This dynamic parameter adjustment enables the system to maintain high measurement precision across the full input voltage range while operating at high speeds.
3Speed
If voltage-to-delay conversion is used, then operating speed is improved, but manufacturing precision deteriorates due to non-linear response
Solution Approach 1:
The feedback loop takes the digital output from the TDC stages and feeds it back to the voltage-to-delay converter. This feedback enables the V2D converter to detect and compensate for non-linearities in its conversion response. By continuously adjusting its operation based on the feedback signal, the system maintains linear conversion characteristics across the full input range, ensuring high manufacturing precision while preserving the speed advantages of delay-domain conversion.
Data Source
AI summary
A delay-domain analog-to-digital converter including a voltage-to-delay circuit and a time-to-digital converter circuit, and a method of calibrating the same. The voltage-to-delay circuit generates a delay signal based on applied calibration voltage, and the delay signal is applied to a first residue stage configured to generate a sign bit and a residue delay signal. The residue delay signal is applied to an input of a successive residue stage, which is configured to generate a sign bit and provide a residue delay signal to inputs of a next successive residue stage. First and second trim circuits are provided in a delay comparator of one of the successive residue stages, and configured to adjust a first response of the residue stage for a calibration voltage in a first range, and to adjust a second response of the residue stage for a calibration voltage in a second range.