SAR ADC Settling Time Calibration for Accurate Bit Comparisons
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Solution Overview
Problem
The inconsistent settling time after each bit flip in a digital-to-analog converter of a successive-approximation register ADC leads to comparator errors and conversion inaccuracies due to inconsistent delay times in the comparison process.
Innovation Solution
A calibration method is implemented to determine and adjust the settling time after each bit flip, using a calibration controller to record and compensate for capacitor mismatches, ensuring accurate comparison signals by adjusting the digital code based on the comparator's threshold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the settling time is not calibrated for each bit flip, then the conversion speed is faster, but the comparison accuracy deteriorates due to inconsistent delay times
Solution Approach 1:
The patent applies preliminary action by performing settling time calibration before actual conversion operations. The calibration controller pre-determines the settling times for different bit flip scenarios (single bit, two bits, three bits) and stores these values for subsequent use during normal conversion, ensuring accurate comparisons without adding delay to the actual conversion process
Solution Approach 2:
The patent implements dynamics by making the delay time adjustable and adaptive based on the number of bits flipped. The successive-approximation controller dynamically selects different delay times from calibration data depending on whether 1, 2, or 3 bits are flipped, optimizing both accuracy and speed for each specific conversion scenario
2Measurement precision
If the settling time is calibrated for each bit flip, then the comparison accuracy is improved, but the device complexity increases due to additional calibration components
Solution Approach 1:
The patent merges the calibration function with the existing successive-approximation controller by integrating a calibration controller that shares the same digital-to-analog converter and comparator resources. This consolidation allows settling time calibration to be performed using existing hardware components without adding significant complexity to the system
Solution Approach 2:
The system performs self-calibration by automatically determining settling times for different bit flip scenarios without requiring external calibration equipment. The calibration controller autonomously executes calibration sequences and stores the results for use during normal operation, making the system self-sufficient
Data Source
AI summary
A successive-approximation register analog-to-digital converter includes a first digital-to-analog converter, a comparator, a successive-approximation controller, and a calibration controller. The first digital-to-analog converter generates a difference voltage based on an input voltage and a digital code. The digital code corresponds to a sum of the input voltage and the difference voltage. When the difference voltage exceeds a threshold, the comparator sets a comparison signal to an enabled state. The successive-approximation controller adjusts the digital code based on the comparison signal, so that the digital code corresponds to the input voltage. The calibration controller executes a calibration process to determine a delay time from the digital code changing to the comparison signal switching from a disabled state to the enabled state.