Time-Interleaved SAR ADC Calibration for Capacitor and Timing Errors
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Solution Overview
Problem
Time-interleaved successive approximation register analog-to-digital converters (TISAR ADCs) face challenges in achieving high accuracy and speed due to capacitance errors and time errors, which are exacerbated by mismatch and capacitor array errors, limiting their performance in wireless communication applications.
Innovation Solution
A calibration method that jointly calibrates capacitor array errors and time errors by using a reference digital signal to adjust capacitor arrays and time delays in TISAR ADCs, reducing mutual influence and improving accuracy and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If time-interleaved SAR ADCs are used to increase conversion rate, then productivity is improved, but manufacturing precision deteriorates due to capacitance errors and time errors
Solution Approach 1:
The patent applies preliminary action by performing calibration before normal conversion operations. A calibration phase is executed first to determine correction values for capacitance errors and time errors in each sub-ADC channel. These pre-calculated correction values are then stored and applied during subsequent conversion operations, allowing the system to maintain high conversion rates while compensating for manufacturing precision issues through advance preparation.
Solution Approach 2:
The patent utilizes parameter changes by adjusting capacitance values and time delay parameters through calibration. The calibration process varies capacitance activation patterns and time delay settings across different calibration phases to independently characterize and correct capacitance errors and time errors. This parameter adjustment approach enables the system to optimize conversion accuracy without affecting the high conversion rate capability of the time-interleaved architecture.
2Productivity
If multiple SAR ADCs operate simultaneously in time-interleaved mode, then productivity is improved, but device complexity increases due to mismatch and capacitor array errors
Solution Approach 1:
The patent implements feedback by using the output signals from multiple time-interleaved sub-ADCs as input to a calibration module. The calibration module processes these output signals to generate correction values that are fed back to adjust the operation of each sub-ADC. This feedback mechanism continuously monitors and corrects for mismatches and capacitor array errors, allowing the system to maintain high productivity while managing device complexity through automated error compensation.
Solution Approach 2:
The patent introduces an intermediary calibration module that mediates between the multiple time-interleaved sub-ADCs and the final output. This calibration module acts as an intermediate processing stage that receives signals from all sub-ADCs, performs calibration calculations to determine correction values for capacitance and time errors, and generates corrected output signals. The intermediary approach isolates the complexity of error management from the core conversion function, enabling high productivity while systematically handling device complexity.
3Measurement precision
If calibration is performed to improve accuracy, then measurement precision is improved, but loss of time occurs during calibration process
Solution Approach 1:
The patent applies preliminary action by performing calibration before normal conversion operations. A calibration phase is executed first to determine correction values for capacitance errors and time errors in each sub-ADC channel. These pre-calculated correction values are then stored and applied during subsequent conversion operations, allowing the system to maintain high conversion rates while compensating for manufacturing precision issues through advance preparation.
Solution Approach 2:
The patent utilizes periodic action by implementing calibration at specific intervals rather than continuously. The calibration process is performed periodically to update correction values, and these values are then used for an extended period until the next calibration cycle. This periodic approach balances the need for accurate measurement with the constraint of time loss, as calibration is performed only when necessary to maintain conversion accuracy without continuously interrupting normal operations.
Data Source
AI summary
Provided are a Time-Interleaved Successive Approximation Register Analog-to-Digital Converter, TISAR ADC, and a calibration method thereof. The calibration method for the TISAR ADC may include: sampling an analog signal input into the TISAR ADC to generate a reference digital signal (S130); according to the reference digital signal and output digital signals generated by analog-to-digital conversion sub-modules of the TISAR ADC, obtaining capacitor array calibration parameters and time delay calibration parameters of the analog-to-digital conversion sub-modules; adjusting capacitor arrays of the corresponding analog-to-digital conversion sub-modules according to the capacitor array calibration parameters, respectively; and adjusting time delays of the corresponding analog-to-digital conversion sub-modules according to the time delay calibration parameters, respectively.