Time-Interleaved ADC Timing Calibration Using Progressive Correlation
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Solution Overview
Problem
High-speed analog-to-digital converter (ADC) circuits using multiple ADCs in a time-interleaving manner suffer from data distortion due to time skew errors, degrading performance.
Innovation Solution
An ADC circuit with a control logic circuit that calculates correlation values between data output from multiple ADCs using varying numbers of bits and times to calibrate sampling timing, minimizing power consumption and time required for calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple ADCs are used in a time-interleaving manner to enhance conversion speed, then the conversion speed is improved, but time skew errors between ADCs cause data distortion and performance degradation
Solution Approach 1:
The patent changes the parameter of correlation calculation by using different numbers of bits (first number of bits vs. second number of bits) and different numbers of times (first number of times vs. second number of times) to calculate correlation values at different calibration stages. This progressive refinement approach adjusts the calculation parameters to balance speed and accuracy requirements.
2Reliability
If calibration methods are used to correct sampling timing, then time skew errors are reduced, but power consumption and calibration time increase
Solution Approach 1:
The patent applies partial action by performing correlation calculations with different numbers of bits and different numbers of times at different calibration stages. Instead of always using maximum precision calculations, the system uses fewer bits and fewer iterations when appropriate, reducing power consumption while still achieving the required calibration accuracy.
Solution Approach 2:
The patent changes calculation parameters (number of bits, number of times) based on calibration stage requirements. During initial calibration, fewer bits and fewer iterations are used to reduce power consumption, while final precision calibration uses more bits and more iterations to ensure accuracy.
3Measurement precision
If high-precision correlation calculations are performed to ensure calibration accuracy, then sampling timing accuracy is improved, but the time required for calibration increases
Solution Approach 1:
The patent uses partial action by performing correlation calculations with different numbers of bits and different numbers of times at different calibration stages. Instead of always using maximum precision calculations, the system uses fewer bits and fewer iterations when appropriate, reducing calibration time while still achieving the required calibration accuracy.
Data Source
AI summary
An ADC circuit including: ADCs to perform conversion operations in a time-interleaving manner; and a control logic circuit connected to the ADCs, wherein the control logic circuit is configured to: calculate a correlation value between data output from the ADCs a first number of times using a first number of bits among each bit of the data; calibrate a sampling timing of at least some of the ADCs, based on a first cumulative correlation value, which is obtained by accumulating correlation values calculated the first number of times; calculate the correlation value between the data a second number of times by using a second number of bits in each of the data; and calibrate the sampling timing of the at least some of the ADCs, based on a second cumulative correlation value, which is obtained by accumulating correlation values calculated the second number of times.