SAR ADC Architecture for PAM-6 Receivers With Fewer Comparators
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Solution Overview
Problem
Conventional analog-to-digital converters for pulse amplitude modulation (PAM)-6 receivers require seven comparators and seven reference voltages, occupying a large area and consuming high power.
Innovation Solution
A successive approximation analog-to-digital converter for PAM-(2N−2) receivers that uses a switch circuit, conversion circuit, comparison circuit, register, and controller to convert an analog input signal into a digital output signal, reducing the number of comparators and reference voltages while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional analog-to-digital converter design is used for PAM-6 receiver, then conversion accuracy is maintained, but the device occupies large area and consumes high power
Solution Approach 1:
The patent merges multiple capacitor groups into a shared capacitor array that serves all comparators. Instead of having separate capacitors for each of the 7 comparators, a single set of capacitors is shared across all comparators through multiplexing, significantly reducing the total capacitor count and thus the device area while maintaining the required conversion precision
Solution Approach 2:
The capacitor group is designed to be universal and multi-functional, serving multiple comparators simultaneously. The same capacitor array is reused across different comparison operations and different signal paths, allowing the hardware to perform multiple functions with a single component set, thereby reducing overall device area
2Measurement precision
If conventional analog-to-digital converter design is used for PAM-6 receiver, then conversion accuracy is maintained, but power consumption is high
Solution Approach 1:
By merging the capacitor resources into a shared pool that serves all comparators, the patent reduces the total number of active components that consume power. The shared capacitor array eliminates redundant capacitance structures, directly reducing static power consumption while maintaining the precision required for accurate analog-to-digital conversion in PAM-6 receivers
3Area of stationary object
If the number of comparators is reduced to three, then device area and power consumption are reduced, but conversion capability must be maintained
Solution Approach 1:
The patent implements dynamic resource allocation where the three comparators and shared capacitor array are dynamically configured to handle different conversion scenarios. The system dynamically switches between different comparison modes and capacitor configurations to maintain full conversion capability despite having fewer physical comparators, ensuring reliability is preserved through flexible, adaptive operation rather than static redundancy
4Area of stationary object
If shared capacitor groups are used, then device area is reduced, but circuit complexity increases
Solution Approach 1:
The patent introduces control logic as an intermediary that manages the shared capacitor array and coordinates the three comparators. This control intermediary handles the complexity of resource sharing, capacitor switching, and comparator coordination, isolating the complexity from the core conversion function while enabling area reduction through efficient resource management
Data Source
AI summary
A successive approximation ADC includes a switch circuit, a conversion circuit, a comparison circuit and a controller. The conversion circuit outputs first and second comparison voltages that are respectively equal to first and second input voltages when the switch circuit operates in an ON state. The comparison circuit compares the first and second comparison voltages to generate first and second comparison signals. Generation of least significant bits of the first and second comparison signals is related to two first capacitors and two second capacitors of the conversion circuit. When the other bits of the first comparison signal have identical logic values, the controller provides two different voltages respectively to the first capacitors and respectively to the second capacitors; and when otherwise, the controller provides one of the voltages to both of the first capacitors, and provides the other one of the voltages to both of the second capacitors.