On-Chip ADC Dynamic Testing With Built-In Sine Wave Generation

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Solution Overview

Problem

The existing methods for testing Analog-to-Digital Converters (ADCs) rely on external tester equipment, which increases testing costs and limits parallelism, making it difficult to achieve high test efficiency during production and post-production.

Innovation Solution

An integrated circuit (IC) with a built-in test circuit capable of performing on-chip ADC performance testing, including dynamic testing by generating a coherent staircase sine wave, which eliminates the need for external testers and allows for testing during production and post-production.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If external tester equipment is used for ADC testing, then measurement precision can be achieved, but device complexity and testing cost increase

Engineering Contradiction:
ImproveADC performance measurement precisionVSAvoidtesting system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The ADC testing system performs self-testing by generating test signals internally through a signal generator and analyzing the ADC output through a spectrum analyzer integrated in the same device. This eliminates the need for external tester equipment while maintaining measurement precision through built-in self-test circuitry

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The signal generator is designed to generate multiple types of test signals (sine waves, staircase waves, random sequences) and the system can test multiple ADC channels simultaneously. This multi-functional approach allows a single device to perform various ADC testing functions that previously required separate external equipment

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If external tester equipment is used for ADC testing, then measurement precision is maintained, but productivity decreases due to limited test parallelism

Engineering Contradiction:
ImproveADC performance measurement precisionVSAvoidtest parallelism
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The testing system is divided into independent functional modules including signal generator, spectrum analyzer, and multiple ADC test channels. Each channel can operate independently and simultaneously, enabling parallel testing of multiple ADCs without interfering with measurement precision through modular architecture

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system transitions from sequential single-channel testing to multi-dimensional parallel testing by adding multiple independent test channels that can simultaneously evaluate multiple ADC devices. This dimensional expansion from 1D to ND testing dramatically increases productivity while maintaining precision through synchronized operation

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If built-in self-test circuitry is implemented, then productivity increases through high parallelism, but device complexity increases

Engineering Contradiction:
Improvetest parallelismVSAvoidintegrated circuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The signal generator and spectrum analyzer functions are merged into the same integrated circuit device along with the ADC under test. This consolidation enables high test parallelism by allowing multiple ADC channels to be tested simultaneously within a single chip, reducing the need for external equipment while managing complexity through integration

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The test circuitry is nested within the ADC device structure, with the signal generator and spectrum analyzer functions integrated into the same chip as the ADC channels. This nested architecture allows the testing functionality to be embedded within the device being tested, achieving high parallelism while containing complexity within a unified integrated structure

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentEP4089924A1Analog-to-digital converter (ADC) testing
Publication Date: 2022.11.16 NXP BV
  • EP4089924A1 patent drawingFigure 1
  • EP4089924A1 patent drawingFigure 2
  • EP4089924A1 patent drawing

AI summary

An integrated circuit device includes a digital sine wave generator configured to produce portions of a digital sine wave, a combiner circuit configured to output each of the portions of the digital sine wave combined with a respective calibration code during operation in a post-production dynamic test mode, a digital to analog converter (DAC) configured to output an analog sine wave based on the output of the combiner circuit, and a test analog to digital converter (ADC) including an input terminal directly connected to the output of the DAC, and configured to generate a second digital sine wave based on the analog sine wave.