Time-Interleaved ADC Clock Delay Alignment for Gain Calibration
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Solution Overview
Problem
Existing time-interleaved analog-to-digital converters face inaccuracies in gain calibration due to sampling time mismatches and gain mismatches among channels, which are exacerbated by process variations and other factors.
Innovation Solution
A time-interleaved analog-to-digital converter system that includes sampling circuits, amplifier circuits, analog-to-digital converter circuits, and detector circuitry. The detector circuitry adjusts the delay time of clock signals and calibrates the gains of amplifier circuits based on digital signals to reduce sampling time mismatches and improve gain calibration accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If fixed sequence sampling is used in time-interleaved ADC, then sampling operation is simple, but sampling time mismatches occur due to clock signal skew leading to reduced gain calibration accuracy
Solution Approach 1:
The patent applies preliminary action by adjusting the delay time of clock signals before the sampling operation to compensate for timing mismatches. The detector circuitry预先 adjusts the delay time of each channel's clock signal to align sampling time points, ensuring accurate gain calibration without changing the fixed sequence sampling structure.
Solution Approach 2:
The patent changes the delay time parameter of clock signals to compensate for timing mismatches. By adjusting the delay time of each channel's clock signal, the system aligns sampling time points across channels, thereby improving gain calibration accuracy while maintaining the simple fixed sequence sampling operation.
2Productivity
If number of channels is increased to improve sampling rate, then productivity increases, but gain mismatches among channels increase due to process variations
Solution Approach 1:
The patent implements feedback through the detector circuitry that measures the output signals from each channel and uses this information to adjust delay times and compensate for gain mismatches. This closed-loop feedback mechanism enables the system to maintain high sampling rates with multiple channels while correcting gain inconsistencies caused by process variations.
Solution Approach 2:
The patent adjusts the delay time parameter of clock signals for each channel based on detected gain mismatches. By dynamically changing the delay time parameter, the system compensates for gain variations among channels, allowing high-channel-count operation that maintains both high sampling rate and gain consistency.
3Device complexity
If sampling time points are not aligned due to clock mismatches, then device complexity is reduced, but calculation accuracy of gain calibration circuits deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the delay time of clock signals before sampling to align sampling time points. This preliminary timing alignment ensures that subsequent gain calibration calculations are performed on properly synchronized data, improving calculation accuracy without adding complex real-time synchronization mechanisms.
Solution Approach 2:
The patent introduces delay time adjustment as an intermediary mechanism between the clock signals and sampling operation. This intermediary delay adjustment aligns sampling time points across channels, serving as a mediator that resolves timing mismatches and enables accurate gain calibration calculations without increasing overall system complexity.
Data Source
AI summary
A time-interleaved analog-to-digital converter includes sampling circuits, amplifier circuits, analog-to-digital converter circuits, and a detector circuitry. The sampling circuits are configured to an input signal according to first clock signals, to generate first signals. The amplifier circuits are configured to generate second signals according to the first signals. The analog-to-digital converter circuits are configured to convert the second signals to generate a digital signals. The detector circuitry is configured to adjust a delay time of each of the first clock signals, and calibrate gains of the amplifier circuits according to the digital signals.