Pipelined ADC Error Correction Using PN Code Injection
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Solution Overview
Problem
Pipelined analog-to-digital converters face degradation in spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNDR) due to capacitor mismatch and inter-stage gain errors, particularly in binary code type digital-to-analog converters.
Innovation Solution
A pipelined analog-to-digital converter design incorporating a PN code injection module and digital correction circuit, which generates PN codes to estimate and correct capacitor mismatch and inter-stage gain errors by analyzing mean values of codes outputted by sub-analog-to-digital converters, utilizing a PN code generator and digital correction circuit to adjust the amplifier's inter-stage gain and correct the code output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a binary code type digital-to-analog converter is used in the pipelined ADC, then the conversion speed is improved, but capacitor mismatch errors occur leading to degradation of SFDR and SNDR
Solution Approach 1:
The patent applies preliminary action by injecting PN codes into the ADC system before normal operation to characterize and store capacitor mismatch errors and inter-stage gain errors in lookup tables. This pre-characterization allows the system to compensate for these errors during conversion without interrupting normal operation, thus maintaining high conversion speed while improving SFDR and SNDR performance.
Solution Approach 2:
The patent implements feedback by using the PN code injection to measure actual capacitor values and gain errors, then storing these measurements in lookup tables that are referenced during normal conversion. The system continuously monitors and corrects for errors by comparing expected versus actual behavior, feeding this information back into the correction process to maintain precision without sacrificing speed.
2Measurement precision
If capacitor mismatch and inter-stage gain errors are corrected using traditional methods, then the SFDR and SNDR are improved, but the conversion process requires interruption
Solution Approach 1:
The patent performs error characterization and correction parameter calculation in advance by injecting PN codes during idle periods or initialization phases, storing the results in lookup tables. This preliminary action enables error correction to be applied during normal conversion without interrupting the conversion process, thus improving SFDR and SNDR while maintaining conversion throughput.
Solution Approach 2:
The patent implements periodic PN code injection to update error characterization data at scheduled intervals rather than continuously interrupting conversion. This periodic approach allows the system to maintain high productivity during normal operation while periodically refreshing correction parameters to adapt to drift or environmental changes, thus improving precision without significantly impacting throughput.
3Measurement precision
If correction precision is increased to improve error compensation, then the power consumption increases
Solution Approach 1:
The patent applies partial action by implementing correction for only the most significant error sources (capacitor mismatch and inter-stage gain errors) rather than attempting to correct all possible errors. The lookup tables store correction data at selected precision levels, providing sufficient correction accuracy to improve SFDR and SNDR while avoiding the excessive power consumption that would result from attempting to correct all error sources with maximum precision.
Data Source
AI summary
The disclosure belongs to the field of integrated circuit technologies, and particularly relates to a pipelined analog-to-digital converter capable of correcting capacitor mismatch and inter-stage gain errors. According to the disclosure, a PN code is injected into a digital domain or an analog domain of a pipelined sub-analog-to-digital converter, a mean value of codes outputted by a sub-analog-to-digital converter of an (i+1)th pipeline stage in two cases that a PN code is equal to +1 and the PN code is equal to −1 is counted under the condition that a code outputted by a sub-analog-to-digital converter of an ith pipeline stage is b, and a capacitor mismatch error and an actual inter-stage gain of the ith pipeline stage are estimated according to the mean value and a relationship between a capacitor mismatch error and an actual inter-stage gain error of a previous pipeline stage.