Time-Interleaved ADC Calibration for Timing Skew Correction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Time-interleaved analogue-to-digital converters (ADCs) suffer from artefacts due to tolerances in analogue passive circuitry and manufacturing process variations, leading to offset, gain, and timing skew issues.

Innovation Solution

A time-interleaved analogue-to-digital converter operates in both operational and calibration modes, where in calibration mode, the second ADC samples simultaneously or closer in time to the first ADC, allowing for accurate calibration of sample timings and adjustments to correct for offset, gain, and timing skew.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple ADCs are arranged in parallel with time-interleaved sampling, then throughput is improved, but measurement precision deteriorates due to offset, gain, and timing skew errors

Engineering Contradiction:
ImprovethroughputVSAvoidmeasurement precision
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by performing calibration measurements before normal operation. The system first determines offset, gain, and timing skew parameters through calibration mode measurements, then uses these pre-determined parameters to correct subsequent production measurements. This separates the error characterization phase from the data acquisition phase, allowing high-precision corrections to be applied during throughput-critical operations without adding measurement time.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using the measured offset, gain, and timing skew parameters from calibration mode to continuously correct the output of multiple ADCs during operational mode. The system feeds back the characterized error parameters into the signal processing chain, automatically compensating for mismatches between parallel ADCs. This closed-loop approach maintains measurement precision while preserving the throughput benefits of parallel sampling.

Inventive Principle:
Principle #23Feedback

2Productivity

If multiple ADCs sample at different time instants to achieve time-interleaved operation, then productivity is improved, but reliability deteriorates due to timing skew and artefacts

Engineering Contradiction:
ImprovethroughputVSAvoidreliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by performing timing calibration before normal operation. The system first measures the actual timing skew between multiple ADCs during calibration mode, determines the timing offset parameters, and stores these characteristics. During operational mode, these pre-determined timing parameters are used to synchronize or correct the sampled data, ensuring reliable reconstruction of the original signal despite the parallel ADCs sampling at slightly different instants.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using the characterized timing skew parameters to continuously adjust and synchronize the outputs of parallel ADCs. The system feeds back the measured timing offset information into the signal processing chain, applying corrective time-alignments to each ADC's output based on its specific timing characteristics. This ensures that even though ADCs sample at different time instants for throughput, the final reconstructed signal maintains temporal coherence and reliability.

Inventive Principle:
Principle #23Feedback

3Manufacturing precision

If ADCs are calibrated with simultaneous sampling, then manufacturing precision is improved, but device complexity increases due to mode switching and timing control

Engineering Contradiction:
Improvecalibration accuracyVSAvoiddevice complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies dynamics by making the sampling mode adjustable rather than fixed. The system can dynamically switch between calibration mode (with simultaneous sampling for high precision) and operational mode (with time-interleaved sampling for high throughput). The sampling timing is made flexible and controllable, allowing the system to adapt its behavior based on whether calibration or production measurement is required. This dynamic capability resolves the contradiction by allowing high precision during calibration while maintaining high throughput during operation.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements periodic action by alternating between calibration mode and operational mode in time. The system performs calibration measurements periodically (either continuously or at intervals) to update offset, gain, and timing skew parameters, then switches to operational mode for high-throughput data acquisition. This periodic switching allows the system to maintain accurate calibration parameters without permanently sacrificing throughput, and enables recalibration when drift occurs without interrupting normal operations.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20250233598A1Time-interleaved analogue-to-digital converters (ADCS)
Publication Date: 2025.07.17 HAMILTON SUNDSTRAND CORP
  • US20250233598A1 patent drawing
  • US20250233598A1 patent drawing
  • US20250233598A1 patent drawing

AI summary

A time-interleaved analogue-to-digital converter including a first analogue-to-digital converter and a second analogue-to-digital converter, each arranged to sample a respective analogue input periodically and produce a respective digital output based on the sampled analogue input, and also including a signal interleaving portion, arranged to combine the digital outputs to produce a digital output signal. The time-interleaved analogue-to-digital converter is configured for operation both in an operational mode and a calibration mode. In the operational mode, the second analogue-to-digital converter is arranged to sample the analogue input a first time period after the first analogue-to-digital converter samples the analogue input. In the calibration mode, the second analogue-to-digital converter is arranged to sample the analogue input simultaneously with the first analogue-to-digital converter, or a second time period apart from a time at which the first analogue-to-digital converter samples the analogue input. The second time period is shorter than the first time period.