Analogue-Digital Converters TRIZ Cases

Foreground and background calibration align distributed ADC clocks and token signals across PVTE corners without global reset.

A precharging capacitor tracks the ADC input and transfers stored charge to sampling capacitors, cutting driver power while preserving bandwidth.

FIR-based coefficient fitting corrects time-interleaved ADC bandwidth and clock mismatch with lower filter order, less complexity, and less overflow risk.

A sequencer schedules external-channel conversions first and fits internal ad-hoc requests into idle gaps to raise ADC throughput without timing conflicts.

Dither-based clock calibration detects timing skew polarity between interleaved ADCs, improving conversion accuracy across unknown Nyquist zones.

Calibration logic and constant-current discharge improve voltage-to-delay linearity at low supply voltage while preserving high-speed ADC conversion.

FIR preprocessing cleans TI-DAC measurement signals from non-ideal feedback channel interference, improving mismatch calibration accuracy.

Dual-frequency phase detection and correction reduces clock shift errors, improving data recovery in semiconductor receivers.

By splitting the input range into sub-ranges, this ADC cuts area and conversion time while preserving high-resolution digital output.

Edge-triggered channel switching and bus impedance sampling enable bidirectional level shifting and re-driving across voltage domains.

Adaptive quantization levels matched to signal distribution cut low-precision ADC error and improve decoding accuracy.

Short-cycle sampling after a lower-bit second pipeline stage boosts A/D conversion speed while preserving accuracy through reduced feedback load.

By changing converter quantization step size between readings, this case improves ADC and TDC resolution for static signals without added dithering noise.

Wideband FFT screening plus selective cyclostationary analysis improves real-time detection and classification of weak burst signals.

A current-mode MDAC front end with phased current generation reduces clock-skew noise and linearity errors in time-interleaved ADCs.

Judge blocks switch between high and low ADC gain data to extend image sensor dynamic range while cutting power and processing time.

Motion-induced RF occlusion and MTI filtering reveal stationary object locations, building high-resolution environment maps with few antennas.

A phased sampler with faster per-channel ADCs removes rate-matching constraints, simplifying high-speed conversion and improving flexibility.

Local wake-word detection handles routine voice commands on-device, sending audio to the cloud only for specific or unrecognized requests.

A two-phase TIADC calibration flow first corrects offset, gain, and time skew, then uses a reference channel to train neural networks for non-linear mismatch correction.

Dual-sensitivity pixel readout builds HDR frames with less ghosting in moving scenes by adapting sensor capture to the photographing environment.

Digital correction of sub-DAC mismatch errors in CT ADCs cuts noise spectral density and distortion without added analog correction complexity.

A mixed planar transistor and FinFET ADC with auto-zero switching cuts thermal noise and power use while preserving gain and speed.

Shared secondary-latch clocking cuts ADC wiring, footprint, parasitic impedance, and power while keeping latch timing stable.

On-chip switching and ADC measurement test power FET source-drain resistance without probe needles, avoiding parasitic resistance and contamination.

A shared multiplexer, filter, and BIT signal path cuts ADC count while preserving resolver and LVDT position accuracy.

An adaptive capacitor-array gain circuit keeps ADC input levels in range by compensating for temperature, noise, and signal offset.

Delay circuits and added MUTEX logic preserve signal order in TDC converters, limiting metastability errors to at most one bit.

A relay and semiconductor switch in series cut leakage at low currents while keeping fast capacitor discharge for wide-range measurement.

Selective row and column readout targets image sensor ROIs to cut data load and raise frame rates without losing local resolution.

Blind online estimation adapts nonlinearity functions and coefficients to correct high-order RF-ADC distortion with less memory.

Adjacent receiver channels and shared ADC switching help coherent mechanical LiDAR handle scanner angle lag and overlapping returns.

Periodic switching between two AD converters equalizes environmental drift and improves scale displacement accuracy.

Optical switching lets coherent mechanical LiDAR share ADCs across detector channels while compensating scanner angle lag, noise, and offset.

An analog integrator performs ToF convolution in hardware, cutting digital processing load to improve LiDAR resolution and scanning speed.

An on-chip calibration source and switchable input path let interleaved ADC channels self-correct mismatch errors and improve SNR without external setup.

Dual avalanche photodiodes use processor-set bias balancing to reject laser intensity noise and improve LiDAR receiver SNR.

Direct timing-error estimation and slope-based correction remove TI-ADC skew spurs in real time without long convergence or bandwidth limits.

Selective signal extraction and synchronized sampling improve reservoir short-term memory without sacrificing nonlinear transformation performance.

Separate offset calibration and data recovery in a time-interleaved ADC prevent erroneous sample cancellation at specific input frequencies.

A standardized touch data packet captures coordinates and touch size to cut interface overhead and improve automotive touch event handling.

Firmware estimates subADC gain error from stored samples and uses thresholding to reject invalid data, reducing spurs without stopping output.

By subtracting the predicted signal portion before conversion, SAR ADCs can keep high sampling rates with less dynamic-range and power burden.

Dynamic coefficient calculation preserves phase and magnitude accuracy in asynchronously sampled metal detector signals without sync hardware.

Parallel ADC and DAC paths use 180-degree inversion and output combining to cancel conversion spurs and improve signal purity.

A range detector routes strong and weak analog samples through different ADC paths to avoid clipping while preserving signal resolution.

Offset-based correlation calibration maps residue amplifier nonlinear gain in a pipeline ADC to improve output code linearity.

Pre-sampling capacitors shift reference subtraction and input amplification ahead of conversion, cutting ADC power and calibration needs.

Statistical detection of the first signal change improves wireless timing accuracy and shrinks the window for undetected relay attacks.

Calibration mode brings interleaved ADC samples closer together to correct offset, gain, and timing skew without sacrificing throughput.

A holed first mirror and vertically moving second mirror enable compact point measurement while fixed sampling stabilizes LiDAR timing.

Controller-applied configuration and calibration data let an ADC change operating modes without rebooting, cutting switch time and disruption.

A digital replica of the continuous-time filter calibrates path mismatch in a pipeline ADC, improving reconstruction accuracy and analog gain.

Frequency-modulated ultrasonic pulses with time gating improve distance resolution and reduce air propagation errors in object location sensing.

Per-channel neural correction compensates gain and offset mismatch in time-interleaved ADCs, cutting noise and improving output accuracy.

A jitter-capturing ADC derives calibration values from clock phase noise, then subtracts sampling error to improve high-speed conversion accuracy.

A shared calculator and comparator let a two-bit SAR ADC improve resolution while cutting converter area and complexity in embedded systems.

Low-frequency offsets from analog front ends and ADCs are detected with IIR filtering and subtracted in real time for stable measurements.

Time-domain waveform matching stabilizes laser echo timing, improving ranging precision, SNR, and test frequency with simpler circuitry.

SAR-programmed clock delays and overlapping multi-phase sampling reduce channel timing skew, spurious tones, and dynamic-range loss in interleaved ADCs.

High-pass shaped dither cuts quantization-error distortion in CT ADC residue generation while preserving error correction range.

Aggregating samples across symbol periods detects the earliest signal change more precisely, improving synchronization and limiting relay attack exposure.

Pulse-edge-triggered sampling detects and compensates phase deviation in absolute encoder sine/cosine signals without high AD sampling ratios.

Dynamic A/D resolution adjustment matches converter range to actual signal levels, improving transmitter measurement accuracy across varying sensor spans.

Multiple slope generators and switchable conversion modes cut offset and gradient errors while balancing SNR and ADC accuracy.

A split sub-ADC scheduling scheme enables TI-ADC error estimation without disrupting conversion, improving SFDR and reducing image effects.

A sampling capacitor powers a controlled oscillator during readout, cutting ADC area and power while preserving conversion accuracy.

Using body bias in a current-starved current-mirror VTC expands rail-to-rail input range while preserving linearity and low power.

Randomly skipping samplers in a time-interleaved ADC spreads mismatch errors, reducing timing skew distortion without continuous recalibration.

A low-resolution reference ADC tracks polarity and zero-crossing error to calibrate interleaved sub-ADCs with low power and less distortion.

Determining the MSB while a sub-ADC samples the input shortens pipelined ADC conversion time and lowers comparator count and power use.

Reconfigurable analog and digital arrays balance real-time signal precision, speed, and power through coordinated mixed-signal computing.

Analyzes even-period timing differences in interleaved ADC outputs to cut clock skew, power use, and calibration time near Nyquist frequency.

By reusing interleaved ADC quantized outputs, this case cuts clock skew without extra calibration circuits, reducing power use and calibration time.

Odd-ratio test-signal sampling calibrates time skew in interleaved ADC stages with simple logic, avoiding extra reference circuits.

A synthesized delay stage replaces RC lattice delay lines in pipeline ADCs to extend flat-delay bandwidth for OSR 4 and above.

Multiple low-speed sub-Nyquist ADC channels estimate broadband signal frequency across a wider range without costly high-speed converters.

A square wave reference and switchable input path calibrate timing skew in time-interleaved ADCs without sacrificing aggregate sampling rate.

Phase detectors align replica DAC clocks to a MUX clock zero crossing, reducing mismatch and enabling higher sampling rates.

Relative-timing interpolation between comparators enables direct RF sampling ADCs to remove mixers and local oscillators while cutting hardware and power.

I/Q correction paths adjust ADC clock sampling to suppress crosstalk and multiplicative jitter, improving transceiver dynamic range.

Dual sampling capacitors enable continuous charge-to-digital conversion without redistribution breaks, cutting delay, energy use, and converter area.

A feedforward path filters and subtracts unwanted frequencies to improve ADC anti-aliasing without raising THD or area cost.

Polling groups ADC sampling points by candidate interval to reject noise and deliver faster signal output with lower latency.

Multiple SAR controllers determine digital bits in parallel, reducing ADC conversion time as output resolution increases.

A two-stage JFET PGIA with selectable resistor strings gives ADC front ends variable gain, high input impedance, and low distortion.

Adaptive sampling based on rough distance estimates cuts aliasing and filtering effort, enabling mm-level precision ranging.

Feedback from the controlled oscillator captures PWM timing error to improve ring-oscillator ADC linearity and cut audio distortion.

Synchronizing the chopping sequence with the observation window enables dual-loop calibration of switch time skew while limiting noise in interleaved ADCs.

Programmable channels with switching, ADC/DAC paths, and calibration let one sensor platform handle multiple analog sensor types.